参数资料
型号: IR3529MTRPBF
厂商: International Rectifier
文件页数: 12/22页
文件大小: 0K
描述: IC CTRL XPHASE CPU/ASIC 20-MLPQ
标准包装: 1
系列: XPhase3™
应用: 处理器
电流 - 电源: 2mA
电源电压: 8 V ~ 16 V
工作温度: 0°C ~ 125°C
安装类型: 表面贴装
封装/外壳: 20-MLPQ
供应商设备封装: 20-MLPQ(4x4)
包装: 标准包装
其它名称: IR3529MTRPBFDKR
IR3529
share adjust amplifier of the phase will pull up the starting point of the PWM ramp thereby decreasing its duty cycle and
output current. The current share amplifier is internally compensated so that the crossover frequency of the current
share loop is much slower than that of the voltage loop and the two loops do not interact. For proper current sharing
the output of current sense amplifier should not exceed (VCCL-1.4V) under all operating condition.
IR3529 THEORY OF OPERATION
Block Diagram
The Block diagram of the IR3529 is shown in Figure 5, and specific features are discussed in the following
sections.
PHSIN
D
Q
PSI_SY NC
PHSOUT
CLKIN
PSI_SY NC
.
OC
.
CLK
QB
PSI_SY NC#
.
.
.
D
Q
.
Turbo
.
CLK
BOOST
.
.
.
.
.
EAIN
.
PWM Comparator .
PGND
GATEL
SW
GATEH
Non-Overlap
Time Generator
.
.
.
.
.
.
.
.
GATEH
Enable
.
GATE H
Driver
VCCL
GATEH
Cycle-by-
VCC
VCC
.
&
Latch .
OC
.
.
Cycle OCP .
200uA
OCSET
. OC
PWM_RESET
100mV
200mV
BODY BRAKING
COMPARATOR
VCCL
SW
LGND
.
.
.
.
.
GATEL
Enable
.
GATE L
GATEL
0.8V
OVP
COMPARATOR
PSI_SY NC#
PSI_SY NC
.
.
SHIFT
Pulse
Generation
.
SHIFT
Driver
SHIFT
PGND
SHIFT
ILL
ISHARE
VCCL
-
+
OVP
.
.
.
Negative Current
Comparator &
DEBUG
COMPARATOR 0.15V VCCL
Amplifier .
.
. . .
Share Adjust
.
.
Latch
.
Synchronous
Rectification
.
0.75 DACIN
CALIBRATION
PHSIN
PSI_SY NC
CURRENT SENSE
AMPLIFIER
Disable
.
.
CSREF
. +
CSAOUT
-
X33
+
CSIN-
CSIN+
DACIN
.
+
CALIBRATION
PHSIN
.
PSI# Comparator
&
8 Count Delay
.
PSI#
IC and activating Body Braking . The IR3529 Body Braking
comparator detects the low signal at the EAIN and
Figure 5: Block diagram
Tri-State Gate Drivers
The gate drivers are design to provide a 2A source and sink peak current (Bottom gate driver can sink 4A). An
adaptive non-overlap circuit monitors the voltage on the GATEH and GATEL pins to prevent MOSFET shoot-
through current and minimizing body diode conduction. The non-overlap latch is added to eliminate erroneous
triggering caused by the switching noise. A fault condition is communicated to the phase IC via the control IC’s
error amplifier without an additional dedicated signal line. The error amplifier’s output is driven low in response to
any fault condition detected by the controller, such as VCCL under voltage or output overload, disabling the phase
TM TM
drives the bottom gate output low. This tri-state operation prevents negative inductor current and negative output
voltage during power-down.
Page 12 of 22
February 12, 2010
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