参数资料
型号: IR3529MTRPBF
厂商: International Rectifier
文件页数: 18/22页
文件大小: 0K
描述: IC CTRL XPHASE CPU/ASIC 20-MLPQ
标准包装: 1
系列: XPhase3™
应用: 处理器
电流 - 电源: 2mA
电源电压: 8 V ~ 16 V
工作温度: 0°C ~ 125°C
安装类型: 表面贴装
封装/外壳: 20-MLPQ
供应商设备封装: 20-MLPQ(4x4)
包装: 标准包装
其它名称: IR3529MTRPBFDKR
IR3529
LAYOUT GUIDELINES
The following layout guidelines are recommended to reduce the parasitic inductance and resistance of the PCB
layout; therefore, minimizing the noise coupled to the IC.
? Dedicate at least one middle layer for a ground plane, which is then split into signal ground plane (LGND) and
power ground plane (PGND).
? Separate analog bus (EAIN, DACIN, and IOUT) from digital bus (CLKIN, PSI, PHSIN, and PHSOUT) to
reduce the noise coupling.
? Connect PGND to LGND pins of each phase IC to the ground tab, which is tied to LGND and PGND planes
respectively through vias.
? Place current sense resistors and capacitors (R CS and C CS ) close to phase IC. Use Kelvin connection for the
inductor current sense wires, but separate the two wires by ground polygon. The wire from the inductor
terminal to CSIN- should not cross over the fast transition nodes, i.e., switching nodes, gate drive outputs,
and bootstrap nodes.
? Place the decoupling capacitors C VCC and C VCCL as close as possible to VCC and VCCL pins of the phase
IC respectively.
? Place the phase IC as close as possible to the MOSFETs to reduce the parasitic resistance and inductance of
the gate drive paths.
? Place the input ceramic capacitors close to the drain of top MOSFET and the source of bottom MOSFET. Use
combination of different packages of ceramic capacitors.
? There are two switching power loops. One loop includes the input capacitors, top MOSFET, inductor, output
capacitors and the load; another loop consists of bottom MOSFET, inductor, output capacitors and the load.
Route the switching power paths using wide and short traces or polygons; use multiple vias for connections
between layers.
Page 18 of 22
February 12, 2010
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