参数资料
型号: IRS2552DSPBF
厂商: International Rectifier
文件页数: 17/32页
文件大小: 0K
描述: IC BALLAST CTLR CCFL/EEFL 16SOIC
标准包装: 45
类型: CCFL/EEFL 控制器
频率: 39 ~ 69 kHz
电流 - 电源: 10mA
电流 - 输出: 450mA
电源电压: 10.6 V ~ 15.6 V
工作温度: -40°C ~ 125°C
封装/外壳: 16-SOIC(0.154",3.90mm 宽)
供应商设备封装: 16-SOIC N
包装: 管件
IRS2552D
to F MIN , therefore applying maximum power to the lamps. At this point the burst mode dimming function will be
enabled.
Run Mode
In RUN mode an additional current source ICR_RUN is also switched into the circuit. This causes C R to ramp up
to V CR+ much more rapidly than before. The C R pin is used to provide ignition timing as well as the burst mode
dimming low frequency ramp.
If the output is open circuit a very large voltage develops at the output. This is fed back to the SD pin through
some suitable isolated sensing network such that the voltage at the SD pin will exceed VSDTH during an over-
voltage condition. At this stage the capacitor C D begins to charge through a current source. When VSD >
VSDTH the burst mode dimming function is disabled and the output will be continuous.
If the voltage at SD drops below VSDTH the capacitor C D will be discharged to 0V again. If SD remains above
VSDTH long enough for the C D capacitor voltage to reach VCDMAX or about 5 V then the IRS2552D will shut
down and go into fault mode.
Lamp Current Control
Additionally the half bridge current is monitored at the CS pin so that during running if too much power is
supplied to the lamps the IRS2552D is able to compensate by reducing the oscillator duty cycle while
maintaining the same run frequency. This prevents the lamps from being over driven preventing premature end
of life. When VCS > VCSTH the C D capacitor will begin to charge and the CD pin voltage will rise. As this occurs
the duty cycle will begin to adjust, i.e. the HO on time will become gradually shorter and the LO on time will
become gradually longer. The dead time will remain constant at all times. In this way the power to the output will
be reduced while the frequency remains at f MIN . As the CD voltage rises, the duty cycle will be further reduced. If
VCS then drops below VCSTH then the duty cycle will be regulated at that point and thus the current will be
maintained at this limit. If VCS remains above VCSTH then the voltage will continue to rise on C D until it reaches
VCDMAX, at which point the duty cycle reaches its minimum limit DC MIN and the IRS2552D will enter FAULT
mode, requiring V CC to fall below UVLO- and then rise above UVLO+ in order to re-start.
Frequency, Current, and Dead Time Calculation
The running frequency of the IRS2552D is given by the following formula:
f MIN =
1
2 . 09 ? C T ? R MIN
where V MIN = 5 V, i.e. When the ignition ramp is complete and R MAX has no further effect on the oscillator.
The ignition frequency given by:
f MAX =
1
2 . 09 ? C T ? R MAX
and the dead time is calculated by:
t DT = R DT ? C DT ? ln( 1 . 5 )
t DT = 0 . 405 ? R DT ? C DT
www.irf.com
17
? 2009 International Rectifier
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