参数资料
型号: IRS2552DSPBF
厂商: International Rectifier
文件页数: 20/32页
文件大小: 0K
描述: IC BALLAST CTLR CCFL/EEFL 16SOIC
标准包装: 45
类型: CCFL/EEFL 控制器
频率: 39 ~ 69 kHz
电流 - 电源: 10mA
电流 - 输出: 450mA
电源电压: 10.6 V ~ 15.6 V
工作温度: -40°C ~ 125°C
封装/外壳: 16-SOIC(0.154",3.90mm 宽)
供应商设备封装: 16-SOIC N
包装: 管件
IRS2552D
PCB Layout Tips
Distance between high and low voltage components: It’s strongly recommended to place the components tied to the
floating voltage pins (V B and V S ) near the respective high voltage portions of the device.
Ground Plane: In order to minimize noise coupling, the ground plane should not be placed under or near the high
voltage floating side.
Gate Drive Loops: Current loops behave like antennas and are able to receive and transmit EM noise (see Figure 5).
In order to reduce the EM coupling and improve the power switch turn on/off performance, the gate drive loops must
be reduced as much as possible. Moreover, current can be injected inside the gate drive loop via the IGBT collector-
to-gate parasitic capacitance. The parasitic auto-inductance of the gate loop contributes to developing a voltage
across the gate-emitter, thus increasing the possibility of a self turn-on effect.
Figure 5: Antenna Loops
Supply Capacitor: It is recommended to place a bypass capacitor (C IN ) between the V CC and V SS pins. A ceramic
1 μ F ceramic capacitor is suitable for most applications. This component should be placed as close as possible to
the pins in order to reduce parasitic elements.
Routing and Placement: Power stage PCB parasitic elements can contribute to large negative voltage transients as
the switch node; it is recommended to limit the phase voltage negative transients. In order to avoid such conditions,
it is recommended to 1) minimize the high-side emitter to low-side collector distance, and 2) minimize the low-side
emitter to negative bus rail stray inductance. However, where negative V S spikes remain excessive, further steps
may be taken to reduce the spike. This includes placing a resistor (5 ? or less) between the V S pin and the switch
node (see Figure 6), and in some cases using a clamping diode between V SS and V S (see Figure 7). See DT04-4 at
www.irf.com for more detailed information.
www.irf.com
20
? 2009 International Rectifier
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