参数资料
型号: IS61DDB41M36-250M3
厂商: INTEGRATED SILICON SOLUTION INC
元件分类: DRAM
英文描述: 36 Mb (1M x 36 & 2M x 18) DDR-II (Burst of 4) CIO Synchronous SRAMs
中文描述: 1M X 36 DDR SRAM, 0.35 ns, PBGA165
封装: 15 X 17 MM, 1 MM PITCH, PLASTIC, FBGA-165
文件页数: 12/26页
文件大小: 460K
代理商: IS61DDB41M36-250M3
12
Integrated Silicon Solution, Inc. — 1-800-379-4774
Rev. B
07/09/04
ISSI
36 Mb (1M x 36 & 2M x 18)
DDR-II (Burst of 4) CIO Synchronous SRAMs
Recommended DC Operating Conditions
(T
A
= 0 to +
70°
C)
Parameter
Symbol
Minimum
Typical
Maximum
Units
Notes
Supply voltage
V
DD
1.8 - 5%
1.8 + 5%
V
1
Output driver supply voltage
V
DDQ
1.4
1.9
V
1
Input high voltage
V
IH
V
REF
+0.1
V
DDQ
+ 0.2
V
1, 2
Input low voltage
V
IL
-0.2
V
REF
- 0.1
V
1, 3
Input reference voltage
V
REF
0.68
0.95
V
1, 5
Clocks signal voltage
V
IN - CLK
-0.2
V
DDQ
+ 0.2
V
1, 4
1. All voltages are referenced to V
SS
. All V
DD
, V
DDQ
, and V
SS
pins must be connected.
2. V
IH
(Max) AC = See
0vershoot and Undershoot Timings
.
3. V
IL
(Min) AC = See
0vershoot and Undershoot Timings
.
4. V
IN-CLK
specifies the maximum allowable DC excursions of each clock (K, K, C, and C).
5. Peak-to-peak AC component superimposed on V
REF
may not exceed 5% of V
REF.
0vershoot and Undershoot Timings
PBGA Thermal Characteristics
Item
Symbol
Rating
Units
Thermal resistance junction to ambient (airflow = 1m/s)
R
Θ
JA
TBD
°
C/W
Thermal resistance junction to case
R
Θ
JC
TBD
°
C/W
Thermal resistance junction to pins
R
Θ
JB
TBD
°
C/W
V
DDQ
20% Min Cycle Time
V
DDQ
+0.6V
GND-0.6V
GND
20% Min Cycle Time
Overshoot Timing
Undershoot Timing
V
IH
(Max) AC
V
IL
(Min) AC
相关PDF资料
PDF描述
IS61DDB42M18 36 Mb (1M x 36 & 2M x 18) DDR-II (Burst of 4) CIO Synchronous SRAMs
IS61DDB42M18-250M3 36 Mb (1M x 36 & 2M x 18) DDR-II (Burst of 4) CIO Synchronous SRAMs
IS61LF12832A 128K x 32, 128K x 36, 256K x 18 4 Mb SYNCHRONOUS FLOW-THROUGH STATIC RAM
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