参数资料
型号: IS61DDB41M36-250M3
厂商: INTEGRATED SILICON SOLUTION INC
元件分类: DRAM
英文描述: 36 Mb (1M x 36 & 2M x 18) DDR-II (Burst of 4) CIO Synchronous SRAMs
中文描述: 1M X 36 DDR SRAM, 0.35 ns, PBGA165
封装: 15 X 17 MM, 1 MM PITCH, PLASTIC, FBGA-165
文件页数: 7/26页
文件大小: 460K
代理商: IS61DDB41M36-250M3
Integrated Silicon Solution, Inc. — 1-800-379-4774
Rev. B
07/09/04
7
ISSI
36 Mb (1M x 36 & 2M x 18)
DDR-II (Burst of 4) CIO Synchronous SRAMs
The
Timing Reference Diagram for Truth Table
on page
8
is helpful in understanding the clock and write truth
tables, as it shows the cycle relationship between clocks, address, data-in, data-out, and controls. All read
and write commands are issued at the beginning of
cycles t and t
w
, respectively.
State Diagram
Linear Burst Sequence Table
Burst Sequence
Case 1
Case 2
Case 3
Case 4
SA
1
SA
0
SA
1
SA
0
SA
1
SA
0
SA
1
SA
0
First Address
0
0
0
1
1
0
1
1
Second Address
0
1
1
0
1
1
0
0
Third Address
1
0
1
1
0
0
0
1
Fourth Address
1
1
0
0
0
1
1
0
Power Up
DDR
-II
Write
Dcount = Dcount + 1
NOP
DDR
-II
Read
Dcount = Dcount + 1
Write
Write
Notes:
1. Internal burst counter is fixed as four-bit linear; that is, when first address is A0+0, next internal burst address is A0+1.
2.
Read
refers to read active status with R/W = high.
3.
Write
refers to write active status with R/W = low.
4.
Load
refers to read new address active status with LD = low.
5.
Load
is read new address inactive status with LD = high.
Load New Address
Dcount = 0
Load
Load
Read
Load
Load
Load
Increment
Write Address
Increment
Read Address
Always
Always
Write
Read
Dcount = 1
Dcount = 1
Dcount = 2
Load
Dcount = 2
相关PDF资料
PDF描述
IS61DDB42M18 36 Mb (1M x 36 & 2M x 18) DDR-II (Burst of 4) CIO Synchronous SRAMs
IS61DDB42M18-250M3 36 Mb (1M x 36 & 2M x 18) DDR-II (Burst of 4) CIO Synchronous SRAMs
IS61LF12832A 128K x 32, 128K x 36, 256K x 18 4 Mb SYNCHRONOUS FLOW-THROUGH STATIC RAM
IS61LF12832A-6.5B2 128K x 32, 128K x 36, 256K x 18 4 Mb SYNCHRONOUS FLOW-THROUGH STATIC RAM
IS61LF12832A-6.5B2I 128K x 32, 128K x 36, 256K x 18 4 Mb SYNCHRONOUS FLOW-THROUGH STATIC RAM
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