参数资料
型号: IS61NVP204818-166TQ
厂商: INTEGRATED SILICON SOLUTION INC
元件分类: SRAM
英文描述: 2M X 18 ZBT SRAM, 3.5 ns, PQFP100
封装: TQFP-100
文件页数: 19/22页
文件大小: 221K
代理商: IS61NVP204818-166TQ
6
Integrated Silicon Solution, Inc. — www.issi.com
Rev. 00A
05/02/07
IS61NLP102436/IS61NVP102436
IS61NLP204818/IS61NVP204818
SYNCHRONOUS TRUTH TABLE(1)
Address
Operation
Used
CE
CE2
CE
CE2
ADV
WE
BW
BWx
OE
CKE
CLK
Not Selected
N/A
H
X
L
X
L
Not Selected
N/A
X
L
X
L
X
L
Not Selected
N/A
X
H
L
X
L
Not Selected Continue
N/A
X
H
X
L
Begin Burst Read
External Address
L
H
L
H
X
L
Continue Burst Read
Next Address
X
H
X
L
NOP/Dummy Read
External Address
L
H
L
H
X
H
L
Dummy Read
Next Address
X
H
X
H
L
Begin Burst Write
External Address
L
H
L
X
L
Continue Burst Write
Next Address
X
H
X
L
X
L
NOP/Write Abort
N/A
L
H
L
H
X
L
Write Abort
Next Address
X
H
X
H
X
L
Ignore Clock
Current Address
X
H
Notes:
1. "X" means don't care.
2. The rising edge of clock is symbolized by
3. A continue deselect cycle can only be entered if a deselect cycle is executed first.
4.
WE = L means Write operation in Write Truth Table.
WE = H means Read operation in Write Truth Table.
5. Operation finally depends on status of asynchronous pins (ZZ and
OE).
BURST
READ
DESELECT
BURST
WRITE
BEGIN
READ
BEGIN
WRITE
READ
WRITE
READ
WRITE
BURST
DS
READ
DS
READ
WRITE
BURST
WRITE
READ
STATE DIAGRAM
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