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参数资料
| 型号： | IS61SF25616-11B |
| 厂商： | INTEGRATED SILICON SOLUTION INC |
| 元件分类： | SRAM |
| 英文描述： | 256K X 16 CACHE SRAM, 11 ns, PBGA119 |
| 封装： | PLASTIC, BGA-119 |
| 文件页数： | 13/14页 |
| 文件大小： | 147K |
| 代理商： | IS61SF25616-11B |
IS61SF25616
8
Integrated Silicon Solution, Inc. — 1-800-379-4774
PRELIMINARY SR056-1A
05/24/99
ISSI
READ/WRITE CYCLE SWITCHING CHARACTERISTICS (Over Operating Range)
7.5
8
8.5
10
11
Symbol Parameter
Min. Max.
Unit
fMAX
Clock Frequency
—
117
—
100
—
90
—
66
—
50
MHz
tKC
Cycle Time
8.5
—
10
—
11
—
15
—
20
—
ns
tKH
Clock High Time
3
—
4
—
4.5
—
4.5
—
4.5
—
ns
tKL
Clock Low Time
3
—
4
—
4.5
—
4.5
—
4.5
—
ns
tKQ
Clock Access Time
—
7.5
—
8
—
8.5
—
10
—
11
ns
tKQX(1)
Clock High to Output Invalid
2
—
2
—
2
—
2
—
2
—
ns
tKQLZ(1,2)
Clock High to Output Low-Z
0
—
0
—
0
—
0
—
0
—
ns
tKQHZ(1,2)
Clock High to Output High-Z
2
3.5
2
3.5
2
3.5
2
3.5
2
3.5
ns
tOEQ
Output Enable to Output Valid
—
3.5
—
3.5
—
3.5
—
3.5
—
3.5
ns
tOELZ(1,2)
Output Enable to Output Low-Z
0
—
0
—
0
—
0
—
0
—
ns
tOEHZ(1,2)
Output Disable to Output High-Z
—
3.5
—
3.5
—
3.5
—
3.5
—
3.5
ns
tAS
Address Setup Time
2
—
2
—
2
—
2
—
2
—
ns
tSS
Address Status Setup Time
2
—
2
—
2
—
2
—
2
—
ns
tWS
Write Setup Time
2
—
2
—
2
—
2
—
2
—
ns
tCES
Chip Enable Setup Time
2
—
2
—
2
—
2
—
2
—
ns
tAVS
Address Advance Setup Time
2
—
2
—
2
—
2
—
2
—
ns
tAH
Address Hold Time
0.5
—
0.5
—
0.5
—
0.5
—
0.5
—
ns
tSH
Address Status Hold Time
0.5
—
0.5
—
0.5
—
0.5
—
0.5
—
ns
tWH
Write Hold Time
0.5
—
0.5
—
0.5
—
0.5
—
0.5
—
ns
tCEH
Chip Enable Hold Time
0.5
—
0.5
—
0.5
—
0.5
—
0.5
—
ns
tAVH
Address Advance Hold Time
0.5
—
0.5
—
0.5
—
0.5
—
0.5
—
ns
Notes:
1. Guaranteed but not 100% tested. This parameter is periodically sampled.
2. Tested with load in Figure 2.
3. Shaded area = ADVANCE INFORMATION DATA.
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