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参数资料
| 型号： | IS61SF25616-11B |
| 厂商： | INTEGRATED SILICON SOLUTION INC |
| 元件分类： | SRAM |
| 英文描述： | 256K X 16 CACHE SRAM, 11 ns, PBGA119 |
| 封装： | PLASTIC, BGA-119 |
| 文件页数： | 9/14页 |
| 文件大小： | 147K |
| 代理商： | IS61SF25616-11B |
IS61SF25616
4
Integrated Silicon Solution, Inc. — 1-800-379-4774
PRELIMINARY SR056-1A
05/24/99
ISSI
TRUTH TABLE
Address
Operation
Used
CE
CE2
CE2
ADSP
ADSP ADSC
ADSC
ADSC ADV
ADV
ADV Write(2,4) OE
OE
DQ
Deselected, Power-down
None
H
X
L
X
High-Z
Deselected, Power-down
None
L
X
H
L
XXXX
High-Z
Deselected, Power-down
None
L
X
L
XXXX
High-Z
Deselected, Power-down
None
X
H
L
X
High-Z
Deselected, Power-down
None
X
0
X
H
L
X
High-Z
Read Cycle, Begin Burst
External
L
H
L
X
X5
X
High-Z
Read Cycle, Begin Burst
External
L
H
L
H
0
X
Read5
X
High-Z
Write Cycle, Begin Burst
External
L
H
L
H
L
X
Write
X
High-Z
Read Cycle, Continue Burst
Next
X
H
L
Read
L
DQ
Read Cycle, Continue Burst
Next
X
H
L
Read
H
High-Z
Read Cycle, Continue Burst
Next
H
X
H
L
Read
L
DQ
Read Cycle, Continue Burst
Next
H
X
H
L
Read
H
High-Z
Write Cycle, Continue Burst
Next
X
H
L
Write
X
High-Z
Write Cycle, Continue Burst
Next
H
X
H
L
Write
X
High-Z
Read Cycle, Suspend Burst
Current
X
H
Read
L
DQ
Read Cycle, Suspend Burst
Current
X
H
Read
H
High-Z
Read Cycle, Suspend Burst
Current
H
X
H
Read
L
DQ
Read Cycle, Suspend Burst
Current
H
X
H
Read
H
High-Z
Write Cycle, Suspend Burst
Current
X
H
Write
X
High-Z
Write Cycle, Suspend Burst
Current
H
X
H
Write
X
High-Z
PARTIAL TRUTH TABLE
Function
GW
BWE
BW1
BW2
Read
H
X
Read
H
L
H
Write Byte a
H
L
H
Write Byte b
H
L
H
L
Write All Bytes
H
L
Write All Bytes
L
X
NOTES:
1. X = Don't Care. 1 = logic low.
2. Write is defined as either 1.) any
BWx and BWE low or 2.) GW is low.
3.
OE is an asynchronous signal and is not sampled by the clock CLK. OE drives the bus immediately (tOELZ) following OE
going low.
4. On write cycles that follow read cycles,
OE must be negated prior to the start of the write cycle to ensure proper write data
setup times.
OE must also remain negated at the completion of the write cycle to ensure proper write data hold times.
5. This read assumes the RAM was previously deselected.
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相关代理商/技术参数 |
参数描述 |
|---|---|
| IS61SF25618-8.5TQI | 制造商:Integrated Silicon Solution Inc 功能描述:SRAM Chip Sync Single 3.3V 4.5M-Bit 256K x 18 8.5ns 100-Pin TQFP |
| IS61SF25618-8.5TQI-TR | 制造商:Integrated Silicon Solution Inc 功能描述:SRAM Chip Sync Single 3.3V 4.5M-Bit 256K x 18 8.5ns 100-Pin TQFP T/R |
| IS61SF51218T-10TQ | 制造商:Integrated Silicon Solution Inc 功能描述:SRAM Chip Sync Single 3.3V 8M-Bit 512K x 16 10ns 100-Pin TQFP |
| IS61SP12836-133B | 制造商:Integrated Silicon Solution Inc 功能描述: |
| IS61SP12836-133TQ-T | 制造商:Integrated Silicon Solution Inc 功能描述:SRAM Chip Sync Quad 3.3V 4.5M-Bit 128K x 36 4ns 100-Pin TQFP T/R |
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