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参数资料
| 型号： | IS80C52CXXX-16:RD |
| 厂商： | ATMEL CORP |
| 元件分类： | 微控制器/微处理器 |
| 英文描述： | 8-BIT, MROM, 16 MHz, MICROCONTROLLER, PQCC44 |
| 封装： | PLASTIC, LCC-44 |
| 文件页数： | 32/134页 |
| 文件大小： | 3805K |
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127
8011Q–AVR–02/2013
ATmega164P/324P/644P
operation. However, due to the symmetric feature of the dual-slope PWM modes, these modes
are preferred for motor control applications.
The PWM resolution for the phase correct PWM mode can be fixed to 8-bit, 9-bit, or 10-bit, or
defined by either ICRn or OCRnA. The minimum resolution allowed is 2-bit (ICRn or OCRnA set
to 0x0003), and the maximum resolution is 16-bit (ICRn or OCRnA set to MAX). The PWM reso-
lution in bits can be calculated by using the following equation:
In phase correct PWM mode the counter is incremented until the counter value matches either
one of the fixed values 0x00FF, 0x01FF, or 0x03FF (WGMn3:0 = 1, 2, or 3), the value in ICRn
(WGMn3:0 = 10), or the value in OCRnA (WGMn3:0 = 11). The counter has then reached the
TOP and changes the count direction. The TCNTn value will be equal to TOP for one timer clock
cycle. The timing diagram for the phase correct PWM mode is shown on Figure 13-8. The figure
shows phase correct PWM mode when OCRnA or ICRn is used to define TOP. The TCNTn
value is in the timing diagram shown as a histogram for illustrating the dual-slope operation. The
diagram includes non-inverted and inverted PWM outputs. The small horizontal line marks on
the TCNTn slopes represent compare matches between OCRnx and TCNTn. The OCnx Inter-
rupt Flag will be set when a compare match occurs.
Figure 13-8. Phase Correct PWM Mode, Timing Diagram
The Timer/Counter Overflow Flag (TOVn) is set each time the counter reaches BOTTOM. When
either OCRnA or ICRn is used for defining the TOP value, the OCnA or ICFn Flag is set accord-
ingly at the same timer clock cycle as the OCRnx Registers are updated with the double buffer
value (at TOP). The Interrupt Flags can be used to generate an interrupt each time the counter
reaches the TOP or BOTTOM value.
When changing the TOP value the program must ensure that the new TOP value is higher or
equal to the value of all of the Compare Registers. If the TOP value is lower than any of the
Compare Registers, a compare match will never occur between the TCNTn and the OCRnx.
Note that when using fixed TOP values, the unused bits are masked to zero when any of the
R
PCPWM
TOP
1
+
log
2
log
-----------------------------------
=
OCRnx/TOP Update and
OCnA Interrupt Flag Set
or ICFn Interrupt Flag Set
(Interrupt on TOP)
1
2
3
4
TOVn Interrupt Flag Set
(Interrupt on Bottom)
TCNTn
Period
OCnx
(COMnx1:0 = 2)
(COMnx1:0 = 3)
相关PDF资料 |
PDF描述 |
|---|---|
| IS80C52CXXX-16SHXXX:R | 8-BIT, MROM, 16 MHz, MICROCONTROLLER, PQCC44 |
| IS80C52CXXX-25:D | 8-BIT, MROM, 25 MHz, MICROCONTROLLER, PQCC44 |
| IS80C52CXXX-30SHXXX:RD | 8-BIT, MROM, 30 MHz, MICROCONTROLLER, PQCC44 |
| IS80C52CXXX-30SHXXX:R | 8-BIT, MROM, 30 MHz, MICROCONTROLLER, PQCC44 |
| IS80C52CXXX-L16:R | 8-BIT, MROM, 16 MHz, MICROCONTROLLER, PQCC44 |
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