参数资料
| 型号： | ISL12082IUZ-T |
| 厂商： | Intersil |
| 文件页数： | 10/26页 |
| 文件大小： | 0K |
| 描述： | IC RTC I2C LO-POWER 10-MSOP |
| 标准包装： | 2,500 |
| 类型： | 时钟/日历 |
| 特点： | 警报器，闰年，监视计时器 |
| 时间格式： | HH:MM:SS:hh（12/24 小时） |
| 数据格式： | YY-MM-DD-dd |
| 接口： | I²C，2 线串口 |
| 电源电压： | 2.7 V ~ 5.5 V |
| 电压 - 电源，电池： | 1.8 V ~ 5.5 V |
| 工作温度： | -40°C ~ 85°C |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 10-TFSOP，10-MSOP（0.118"，3.00mm 宽） |
| 供应商设备封装： | 10-MSOP |
| 包装： | 带卷 (TR) |
18
FN6731.3
November 24, 2008
Following are the detailed descriptions of the four different
timer modes.
Count Down Timer
The Count Down timer is a basic countdown timer. Once the
timer is enabled by setting TMRE bit to “1”, the TCNT
register is set to the value in TDAT register. The TDAT
register must have a value of two or greater in order for the
timer to start. If the timer is enabled with TDAT register less
than two, then the timer is disabled and the TDAT register
has to be set to an appropriate value before the timer can be
enabled again. The internal TSCNT register increments from
one, and the incremental frequency is set by the TCLK[1:0]
bits. Once the internal TSCNT register overflows, the TCNT
register will decrement by one and the internal TSCNT
register will reset back to one and start counting again until
the TCNT register reaches zero. Once the TCNT register
reaches zero, the timer will issue an interrupt that will set the
TMR status bit to “1” and set the IRQ2 pin to low (if IRQ2E
bit is set to “1”).
When the TIM = “0” (single event mode), the timer stops
after the timer expires. The timer will restart and the IRQ2
pin will be high when the TMR bit is cleared to “0”. The timer
can also be restarted by resetting the TMRE bit to “1” after
setting it to “0”. This method is not recommended since the
TMR status will not clear by this method and may cause
confusion in the system. In single event mode, the time
interval for the timer expiration is calculated by using
Equation 3.
Where, TDAT is the value in the TDAT register. TSDAT is the
value in the TSDAT register (use default if 0). TCLK is the
period set by the TCLK[1:0] bits. For 4kHz setting, please
use 244s for the period. For 100Hz setting please use
10ms for the period.
When the TIM = “1” (periodic interrupt mode), the timer
repeats the countdown function automatically after the timer
expires. The periodic interrupt function can only be
monitored on the IRQ2 pin; therefore, the IRQ2E bit must be
set to “1” to show timer interrupt on the IRQ2 pin. The IRQ2
pin is pulsed each time the timer expires. Once the timer
expires, the TMR status bit set to “1” and the IRQ2 pin goes
low. The internal TSCNT register will reset and continue
counting. Once the internal TSCNT overflows after the timer
expires, the IRQ2 pin will pull back to high but the TMR
status bit will remain at “1” until the user clears it. The TCNT
register will reset back to the value in the TDAT register to
start the new count cycle. The timer will continue counting
until the TMRE = “0” to disable the timer. In periodic interrupt
mode, the time interval for the timer expiration is calculated
differently for the first timer expiration and for the next and
succeeding timer expiration. For the first timer expiration, the
time interval is calculated by using Equation 3. For the next
and succeeding timer expiration, the time interval can be
treated as the high pulse width of IRQ2 pin (THIGH_CDT),
and it is calculated by using Equation 4. The low interrupt
pulse width of IRQ2 pin (TLOW_CDT) is calculated by using
Equation 5. Since the TMR status bit is not reset
automatically by the device at the new count cycle, if the
user resets it, the timer will reset and the next count cycle
will be seen as the first count cycle by the device.
Where, TDAT is the value in the TDAT register. TSDAT is the
value in the TSDAT register (use default if 0). TCLK is the
period set by the TCLK[1:0] bits. For 4kHz setting, please
use 244s for the period. For 100Hz setting please use
10ms for the period.
Where, TSDAT is the value in the TSDAT register (use
default if 0). TCLK is the period set by the TCLK[1:0] bits.
For 4kHz setting, please use 244s for the period. For
100Hz setting please use 10ms for the period.
Since the pulse width of the IRQ2 pin is adjustable with
setting in the TDAT register, the TSDAT register and the
TCLK[1:0] bits, the IRQ2 pin can be use as a variable
frequency/pulse width generator.
Secondary Alarm Timer
The secondary alarm timer function has the exact same
function as the count down timer function except the timer
activates when the device has an alarm interrupt (ALM set to
“1”) with TMRE set to “1” to enable the timer. Once the timer
is activated by the alarm interrupt, the timer will work
independently. Another alarm interrupt will not reset the
timer function while the timer is counting. When the timer is
stopped by the timer interrupt or disabled by the TMRE bit,
the timer has to wait for the new alarm interrupt to activate it.
Please refer to the “Count Down Timer” on page 18 for the
detailed timer function.
Watchdog Timer
The watchdog timer is used as an I2C bus activity monitor. If
the I2C bus does not have an activity for a period of time
which is longer than its normal condition, then the watchdog
timer will issue an interrupt to set the TMR status bit to “1”
and pulse the IRQ2 pin low for 210ms if IRQ2E bit is set to
“1” for timer interrupt. It is recommended to set the IRQ2E to
“1” for IRQ2 pin to show the timer interrupt because the I2C
may be in a fault condition where monitoring the TMR status
bit will be impossible. The watchdog timer is reset and will
start a new count cycle by an I2C “start” condition on the I2C
bus.
The watchdog timer only works with the TCLK[1:0] setting of
“01”, “10” and “11”. The timer is disabled with the TCLK[1:0]
setting of “00”.
Timer Interval = TDAT*TSDAT*TCLK
(EQ. 3)
THIGH_CDT = (TDAT-1)*TSDAT*TCLK
(EQ. 4)
TLOW_CDT = TSDAT*TCLK
(EQ. 5)
ISL12082
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