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| 型号： | ISL5416EVAL1 |
| 厂商： | Intersil |
| 文件页数： | 32/71页 |
| 文件大小： | 0K |
| 描述： | EVALUATION PLATFORM FOR ISL5416 |
| 标准包装： | 1 |
| 类型： | 降频器 |
| 适用于相关产品： | ISL5416 |
| 已供物品： | 板 |
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ISL5416
Tables of Top Level Registers
In the tables below “reset state” indicates the register
contents after a HW reset or a SW hard reset. Unless
noted, a soft channel reset does not clear register
This register controls the output SYNC signal polarity, the
output clock rate and polarity, output data modes, and
channel cascading.
contents. A soft channel reset does clear the slave
registers of a master/slave pair (such as channel data
path control) but does not clear the master.
TABLE 15. COMMON OUTPUT CONTROL FUNCTIONS (GWA = 0000h) RESET STATE = 0x00000001h
P(31:0)
31
30
29
28
27:25
24:21
20
19
18
17
16
15
14
13
12
FUNCTION
ENABLE SERIAL OUTPUT.
1 = serial output mode is enabled. The DOUT parallel data bus is replaced with 4 serial output busses -- one per channel. See 0*06h
- 0*08h and Table 30.
RESERVED. Set to 0.
SCLK RESET.
1 = serial clock divider is reset by SYNCInX if the reset serial output bit is set in IWA = *000h, bits 13 or 29 of any of the 4 channels.
SCLK POLARITY.
1 = Low to High transitions at the center of the data bit.
0 = High to Low transitions at the center of the data bit.
SCLK RATE.
000 = SCLK DIsabled.
001 = input clock rate.
010 = input clock rate / 2.
011 = input clock rate / 4.
100 = input clock rate / 8.
101 = input clock rate /16.
RESERVED. Set to 0.
ROUTE CHANNEL 2 TO CHANNEL 3.
1 = route the output of FIR2 of channel 2 to the input of the CIC to FIR1 gain block in channel 3.
ROUTE CHANNEL 1 TO CHANNEL 2.
1 = route the output of FIR2 of channel 1 to the input of the CIC to FIR1 gain block in channel 2.
ROUTE CHANNEL 0 TO CHANNEL 1.
1 = route the output of FIR2 of channel 0 to the input of the CIC to FIR1 gain block in channel 1.
CHANNEL 0 EXTERNAL AGC SOURCE SELECT.
0 = when bit 14 is set, Channel 1 controls Channel 0 gain.
1 = when bit 14 is set, Channel 3 controls Channel 0 gain.
CHANNEL 2 EXTERNAL/INTERNAL GAIN CONTROL.
1 = Channel 2 gain is controlled by Channel 3.
CHANNEL 1 EXTERNAL/INTERNAL GAIN CONTROL.
1 = Channel 1 gain is controlled by Channel 3.
CHANNEL 0 EXTERNAL/INTERNAL GAIN CONTROL.
1 = Channel 0 gain is controlled by Channel 3 or Channel 1 depending on the state of bit 17.
CLKO2 OR INTRPT .
1 = CLKO2/INTRPT is INTRPT (2 clock period wide pulse).
0 = CLKO2/INTRPT is CLKO2.
NOTE: For INTRPT IWA = 0*0Ah, bit 31 must be set for the channel that is the interrupt source..
FSYNCX POLARITY.
0 = active high
1 = active low.
32
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相关代理商/技术参数 |
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| ISL5416KI | 功能描述:上下转换器 QUAD WIDEBAND DOWN CONVERTER, 256 CABGA RoHS:否 制造商:Texas Instruments 产品:Down Converters 射频:52 MHz to 78 MHz 中频:300 MHz LO频率: 功率增益: P1dB: 工作电源电压:1.8 V, 3.3 V 工作电源电流:120 mA 最大功率耗散:1 W 最大工作温度:+ 85 C 安装风格:SMD/SMT 封装 / 箱体:PQFP-128 |
| ISL5416KIZ | 制造商:Intersil Corporation 功能描述:LEAD-FREE QUAD WIDEBAND DOWN CONVERTER, 256 CABGA - Trays 制造商:Intersil Corporation 功能描述:PB-FREE W/ANNEAL QUAD DIGITAL DOWNCONVER 制造商:Intersil 功能描述:QD WIDEB& DWN CNVRTR 256 CABGA |
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| ISL54200EVAL1Z | 功能描述:EVALUATION BOARD FOR ISL54200 RoHS:是 类别:编程器，开发系统 >> 评估演示板和套件 系列:- 标准包装:1 系列:PCI Express® (PCIe) 主要目的:接口，收发器，PCI Express 嵌入式:- 已用 IC / 零件:DS80PCI800 主要属性:- 次要属性:- 已供物品:板 |
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