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| 型号： | ISL5416EVAL1 |
| 厂商： | Intersil |
| 文件页数： | 54/71页 |
| 文件大小： | 0K |
| 描述： | EVALUATION PLATFORM FOR ISL5416 |
| 标准包装： | 1 |
| 类型： | 降频器 |
| 适用于相关产品： | ISL5416 |
| 已供物品： | 板 |
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ISL5416
TABLE 71. NCO 1 OUTPUT RATE -- TOP 32 BITS (IWA = *011h) RESET STATE = 0x00000000h
P(31:0)
31:0
P(31:0)
31:16
15:0
FUNCTION
RSout(48:16). This NCO sets the re-sampler output sample rate when the IHBF/Resampler block is enabled. If the HOIF is bypassed,
this is 2x the AGC (and FIR2) output rate. NOTE that the re-sampler only interpolates. The re-sampler output can be decimated using
a counter. The decimation is programmed in IWA = *007h, bits 18:16.
Fout = Fs * RSout / (2^48), where RSout = 0 to 2^48 -1, Fout = 0 to ~Fs.
Bits 48:16 of the active register are read back at this location.
If HOIF is enabled, then F out must be ≤ F CLK /2
If IHBF is enabled, HOIF disabled, then F out must be ≤ F CLK
TABLE 72. NCO 1 OUTPUT RATE -- LOWER 16 BITS (IWA = *012h) RESET STATE = 0x00000000h
FUNCTION
RSout(15:0). See IWA = *011h. Bits 15:0 of the active register are read back at this location.
UNUSED.
TABLE 73. NCO 2 INPUT RATE -- TOP 32 BITS (IWA = *013h)
RESET STATE = 0x00000000h
P(31:0)
31:0
FUNCTION
RSin(48:16). This NCO sets the output sample rate for the FIFO (input sample rate to the IHBF/Resampler block) when the
IHBF/Resampler block is enabled. If the HOIF is bypassed, this has no effect.
Fin = Fout * RSin / (2^48), where RSin = 0 to 2^48 -1, Fin = 0 to ~Fout.
Fin should be set equal to the output sample rate of FIR2 (Fs / (CICdeci * FIR1deci * FIR2deci)).
Bits 48:16 of the active register are read back at this location.
TABLE 74. NCO 2 INPUT RATE -- LOWER 16 BITS (IWA = *014h)
RESET STATE = 0x00000000h
P(31:0)
31:16
15:0
FUNCTION
RSin(15:0). See IWA = *013.
Bits 15:0 of the active register are read back at this location.
UNUSED.
Register IWA = *015h is used to add delay to a channel. The output timing is unaffected (except at startup from reset). but the
group delay of the channel is adjusted. If the IHBF and HOIF are both enabled, the total delay range is 0 to 1023/256 FIR2 output
sample periods. NOTE: The HOIF can be enabled with no rate change by setting the NCO2 register (IWA = *013h and *014h) to
zero and setting the bit 22 of IWA = *001h.
TABLE 75. PHASE OFFSET (IWA = *015h) RESET STATE = 0x00000000h
P(31:0)
31:11
10:9
8
7:0
FUNCTION
RESERVED. Set to 0.
FIFO DEPTH. After reset, the FIFO waits until it reaches a depth of 2 + this value (total of 2, 3, 4, or 5) before allowing FIFO reads.
These bits can be used to add delay in increments of the FIR2 output sample rate.
HOIF or IHBF must be enabled.
HOIF INPUT DELAY.
1 = one HOIF input sample delay is added.
HOIF must be enabled.
RESAMPLER PHASE OFFSET. Allows the output sample timing to be shifted in increments of 1/256 the HOIF input period.
00 = least delay.
FF = most delay.
HOIF must be enabled.
54
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相关代理商/技术参数 |
参数描述 |
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| ISL5416KI | 功能描述:上下转换器 QUAD WIDEBAND DOWN CONVERTER, 256 CABGA RoHS:否 制造商:Texas Instruments 产品:Down Converters 射频:52 MHz to 78 MHz 中频:300 MHz LO频率: 功率增益: P1dB: 工作电源电压:1.8 V, 3.3 V 工作电源电流:120 mA 最大功率耗散:1 W 最大工作温度:+ 85 C 安装风格:SMD/SMT 封装 / 箱体:PQFP-128 |
| ISL5416KIZ | 制造商:Intersil Corporation 功能描述:LEAD-FREE QUAD WIDEBAND DOWN CONVERTER, 256 CABGA - Trays 制造商:Intersil Corporation 功能描述:PB-FREE W/ANNEAL QUAD DIGITAL DOWNCONVER 制造商:Intersil 功能描述:QD WIDEB& DWN CNVRTR 256 CABGA |
| ISL54200 | 制造商:INTERSIL 制造商全称:Intersil Corporation 功能描述:USB 2.0 High/Full Speed Multiplexer |
| ISL54200_07 | 制造商:INTERSIL 制造商全称:Intersil Corporation 功能描述:USB 2.0 High/Full Speed Multiplexer |
| ISL54200EVAL1Z | 功能描述:EVALUATION BOARD FOR ISL54200 RoHS:是 类别:编程器，开发系统 >> 评估演示板和套件 系列:- 标准包装:1 系列:PCI Express® (PCIe) 主要目的:接口，收发器，PCI Express 嵌入式:- 已用 IC / 零件:DS80PCI800 主要属性:- 次要属性:- 已供物品:板 |
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