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| 型号： | ISL5416EVAL1 |
| 厂商： | Intersil |
| 文件页数： | 43/71页 |
| 文件大小： | 0K |
| 描述： | EVALUATION PLATFORM FOR ISL5416 |
| 标准包装： | 1 |
| 类型： | 降频器 |
| 适用于相关产品： | ISL5416 |
| 已供物品： | 板 |
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ISL5416
TABLE 36. ADC RANGE CONTROL -- MAIN (IWA = 0*10h) RESET STATE = 0x00000000h (Continued)
P(31:0)
14
13:11
10:8
7:4
3
2
1
0
NOTE:
FUNCTION
TIME USING CLOCKS/SAMPLES.
Count intervals and delays using clocks or input enables.
1 = clocks.
0 = input enables.
UPPER LIMIT.
Upper attenuator control limit, 0 to 42 dB in 6 dB steps.
000 = 0 dB.
111 = 42 dB.
LOWER LIMIT.
Lower attenuator control limit, 0 to 42 dB in 6 dB steps.
000 = 0 dB.
111 = 42 dB.
NORMALIZATION SHIFT/DIVIDE SELECT.
Normalizing shifter control. Divides the integrated magnitude by 2 N prior to threshold comparison:
accumulator input bits: 2 0 . . . 2 -15
accumulator output bits: 2 16 . . . 2 -15
0000 = select 2 1 to 2 -14
1111 = select 2 16 . . .to 2 1
ENABLE INPUT EXPONENT BITS.
Enable the exponent bits from the input to be added to the attenuation control bits and routed to the channel(s).
ENABLE RANGE CONTROL EXPONENT BITS.
Enable the attenuator control register (accumulator MSBs) bits to be added to the exponent bits from the input and routed to the
channel(s).
ENABLE RANGE CONTROL.
1 = enable the range control.
0 = disable the range control (including timers).
ENABLE RANGE CONTROL BITS
Enable changes in the attenuator control register (if this bit is cleared, the timers still run but changes to the register are inhibited.
The range control can be enabled by writing to bit 0 or bit 0 can be set by SYNCInX to start updates. See IWA = 0*05h. Timing reset
by SYNCInX is enabled by bits 0 and 16 of IWA = 0*05h.
TABLE 37. TIME SLOT PERIOD, DELAY FROM SYNCInX TO START OF INTEGRATION (IWA = 0*11h) RESET STATE = 0x00000000h THIS
CONTROL IS SHARED FOR AIN/BIN AND FOR CIN/DIN
P(31:0)
31:16
15:0
FUNCTION
SYNC DELAY.
Delay from SYNC (external or counter generated) to the start of integration. Range of delay is 1 to 65536, load with the desired value
minus 1. Delay in input samples or clocks as selected by bit 14, IWA = 0*10h.
SLOT PERIOD.
Time interval between counter generated SYNCs in samples or clocks as selected by bit 14, IWA = 0*10h. Range for period is 2 to
65536, load with period minus 1.
TABLE 38. NUMBER OF INTEGRATIONS PER SLOT, INTEGRATION TIME (IWA = 0*12h) RESET STATE = 0x00000000h
THIS CONTROL IS SHARED FOR AIN/BIN AND FOR CIN/DIN
P(31:0)
31:16
15:0
FUNCTION
NUMBER OF INTEGRATIONS PER SLOT.
Number of input magnitude integration periods per slot. Range is 1 to 32768, load with number of integrations minus 1.
INTEGRATION TIME.
Number of input samples to average before making an upper or lower threshold decision in samples or clocks as selected by bit 14,
IWA = 0*10h. Range is 2 to 65536, load with samples minus 1.
43
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