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参数资料
| 型号： | ISL5416KI |
| 厂商： | INTERSIL CORP |
| 元件分类： | 无绳电话/电话 |
| 英文描述： | Four-Channel Wideband Programmable DownConverter |
| 中文描述： | TELECOM, CELLULAR, BASEBAND CIRCUIT, PBGA256 |
| 封装： | 17 X 17 MM, PLASTIC, BGA-256 |
| 文件页数： | 17/71页 |
| 文件大小： | 2013K |
| 代理商： | ISL5416KI |
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17
the number of passes in the computation. A listing the
accuracy and gain is provided below.
With maximum gain and with full scale I and Q inputs equal
to ~+/-1.0, the maximum output from the computation is
1.414 * 1.647 = 2.329. The error detector subtracts the
magnitude from the programmable AGC Threshold value.
The AGC Threshold value is set in IWA register *009h and
should be programmed to K times the desired magnitude of
the I/Q where K is the gain of the magnitude computation.
Two adjustment/settling modes are provided in the ISL5416.
In the mean settling mode, the loop adjusts the gain so that
the average magnitude is equal to the programmed set point.
In this mode, the error is scaled by the loop gain and
integrated to compute the forward gain. The loop settles to
the final value asymptotically because the size of the
adjustment decreases as the error decreases. The initial
settling from large errors is fast, but the final pull in is slower.
After the loop has settled, the small adjustment size causes
minimal AM distortion of the signal. The other settling mode
is the median mode. In this mode, the sign of the error is
used increase or decrease the gain by a fixed amount. The
amount of the adjustment is programmed by the loop gain.
The loop settles to the point where there are an equal
number of samples above and below the set point. The loop
settling is roughly linear in dB, but after the loop has settled,
the step size remains the same, so the amount of AM
distortion may be objectionable. The ISL5416 provides two
programmable loop gains, each with a separate attack and
decay settling. The micro-processor can control the loop
gain, or the AGC counters can select the loop gain, so a
large loop gain can be used for initial settling and a smaller
one for tracking. The counters can also select the settling
mode, so the median mode can be used at the beginning of
each time slot and the mean mode used after the initial
settling.
The AGC loop filter is an accumulator (integrator). The
output of the accumulator is the forward gain word that
controls the barrel shifter and multiplier, closing the loop.
There are programmable limits on the accumulator range to
minimize settling time by restricting the AGC to only that
portion of the 96 dB range that is needed. The accumulator
can be loaded by the microprocessor. The gain load is
double buffered-the gain is first loaded into a holding register
by the uP. The gain is then transferred from the holding
register to the accumulator by a write to a special address
location or by the SYNCInX if enabled in IWA *000. The AGC
can be set to a fixed gain either by setting the both upper
and lower gain limits to the desired gain or by setting the
loop gain to zero and programming the accumulator directly.
The bit weighting for the AGC loop is provided in Table 86.
I
TABLE 5. AGC MAGNITUDE COMPUTATION ACCURACY AND
GAIN
PASSES
ERROR +/- (dB)
GAIN
2
0.48
1.581
3
0.13
1.630
4
0.03
1.642
8
0.0001
1.647
ISL5416 AGC Forward Gain Response
0
12
24
36
48
60
72
84
96
0
32768
65536
98304
131072
163840
196608
229376
262144
Code
d
FIGURE 5A. ISL5416 AGC FORWARD GAIN RESPONSE
ISL5416 AGC Forward Gain Response
Magnified View
0
1
2
3
4
5
6
0
2048
4096
6144
8192
10240
12288
14336
16384
Code
d
FIGURE 5B. ISL5416 AGC FORWARD GAIN RESPONSE
MAGNIFIED VIEW (ACTUAL AND IDEAL LINEAR
IN dB)
ISL5416
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