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参数资料
| 型号： | ISL5416KI |
| 厂商： | INTERSIL CORP |
| 元件分类： | 无绳电话/电话 |
| 英文描述： | Four-Channel Wideband Programmable DownConverter |
| 中文描述： | TELECOM, CELLULAR, BASEBAND CIRCUIT, PBGA256 |
| 封装： | 17 X 17 MM, PLASTIC, BGA-256 |
| 文件页数： | 5/71页 |
| 文件大小： | 2013K |
| 代理商： | ISL5416KI |
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5
JTAG
TDO
O
Test data out
TDI
I
PULL UP
Test data in.
TMS
I
PULL UP
Test mode select.
TCLK
I
PULL DOWN
Test clock.
TRST
I
PULL UP
Test reset. Active low. If JTAG not used, tie this pin low. If there is a trace connected to the pin and
there is enough board noise, the JTAG port might get into an unexpected state and stop
communications with the part
OUTPUTS
Aout(15:0)
O
Parallel Data Output bus A. A 16-bit parallel data output which can be programmed to consist of I, Q,
AGC. Data from Channels 0, 1, 2 and 3 can be multiplexed into a common parallel output data bus.
Information can be sequenced in a programmable order. Can be ones complemented. Can be
divided into two 8-bit busses.
See Data Output Formatter Section and Microprocessor Interface
Section. See Table 24.
Bout(15:0)
O
Parallel Data Output bus B. A 16-bit parallel data output which can be programmed to consist of I, Q,
AGC. Data from Channels 0, 1, 2 and 3 can be multiplexed into a common parallel output data bus.
Information can be sequenced in a programmable order. Can be ones complemented. Can be
divided into two 8-bit busses.
See Data Output Formatter Section and Microprocessor Interface
Section.
Cout(15:0)
O
Parallel Data Output bus C. A 16-bit parallel data output which can be programmed to consist of I, Q,
AGC. Data from Channels 0, 1, 2 and 3 can be multiplexed into a common parallel output data bus.
Information can be sequenced in a programmable order. Can be ones complemented. Can be
divided into two 8-bit busses.
See Data Output Formatter Section and Microprocessor Interface
Section.
Dout(15:0)
O
Parallel Data Output bus D. A 16-bit parallel data output which can be programmed to consist of I, Q,
AGC. Data from Channels 0, 1, 2 and 3 can be multiplexed into a common parallel output data bus.
Information can be sequenced in a programmable order. Can be ones complemented. Can be
divided into two 8-bit busses.
See Data Output Formatter Section and Microprocessor Interface
Section.
Below is the table of the serial output bits allocation for DOUT.
Eout(15:0)
O
A 16-bit parallel VGA/Attenuator control output. Partitionable into separate 4 or 8-bit busses.
CLKO1
O
Output Clock 1. Can be programmed to be at CLKC/N for N = 1 to 16. The polarity of CLKO1 is
programmable.
CLKO2/
INTRPT
O
Available ONLY on Rev B (final) version of the part. Provides a complementary output or a second
clock to simplify board routing. Polarity is programmable. It can also be programmed as an interrupt
from one or more channels for a sequenced read (FIFO-like) mode.
See register GWA = 0000h, bit
13.
Pin Descriptions
(Continued)
NAME
TYPE
INTERNAL
PULL-UP/DOWN
DESCRIPTION
SERIAL OUTPUT BITS ALLOCATION
SER. OUTPUT A
SER. OUTPUT B
SER. OUTPUT C
SER. OUTPUT D
SCLKX *
DOUT0
DOUT4
DOUT8
DOUT12
SSYNCX *
DOUT1
DOUT5
DOUT9
DOUT13
SD1X *
DOUT2
DOUT6
DOUT10
DOUT14
SD2X *
DOUT3
DOUT7
DOUT11
DOUT15
* X denotes A, B, C, D as appropriate
ISL5416
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