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参数资料
| 型号： | ISL5416KI |
| 厂商： | INTERSIL CORP |
| 元件分类： | 无绳电话/电话 |
| 英文描述： | Four-Channel Wideband Programmable DownConverter |
| 中文描述： | TELECOM, CELLULAR, BASEBAND CIRCUIT, PBGA256 |
| 封装： | 17 X 17 MM, PLASTIC, BGA-256 |
| 文件页数： | 9/71页 |
| 文件大小： | 2013K |
| 代理商： | ISL5416KI |
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9
ISL5416
VGA/RF Attenuator (A/D Range Control)
The range control section monitors the output of the A/D and
adjusts the RF/IF gain to maintain a desired A/D output
range. The gain adjustments are in 6 dB steps. The levels,
adjustment rates, and gain to bit mapping are
programmable.
The range control section uses three programmable
thresholds. Two thresholds, an upper and a lower threshold,
are compared against the average magnitude of the A/D
output. The range control adjusts the gain to keep the
average A/D output between the upper and lower thresholds.
If the average is above the upper threshold, an internal
attenuator control register is increased by a programmable
amount. If the average is below the lower threshold, the gain
attenuator control register is decreased by a separate
programmed amount. The number of samples averaged for
each decision is programmable. The adjustments to the
attenuator control register can be less than 6 dB to further
filter the inputs. Only the three MSBs of the attenuator
control register are used to control the RF/IF gain, and these
are weighted as 6, 12, 24 dB steps.
The third threshold, an immediate threshold, is compared
against the magnitude of each A/D sample. If the magnitude
of any A/D sample exceeds the threshold, the attenuator
control register is immediately increased by the amount
programmed for the immediate threshold. Because there will
be some time delay from a register change until the effect of
the change is seen at the A/D, the immediate threshold is
disabled for a programmable number of clock cycles after it
has been triggered.
To maximize the input sensitivity the range control also
includes a programmable bias. If the average signal is
between the upper and lower threshold, the bias value is
added from the attenuator control register. This bias
removes attenuation when it is no longer needed to avoid
missing small signals due to high input noise figure.
Four counters control the amount of time that the input is
averaged and align the adjustments to time slot boundaries.
One counts out the time slot period. If desired, this counter
can be reset by a SYNCInX signal to align its count to the
system timing. A second counter provides a programmable
delay from the start of the first counter's period to the start of
the integration period. This compensates for system delays
or allows the adjustments to be made over a certain portion
of the time slot. The third counter sets the integration period
for averaging the input samples for the upper and lower
threshold decisions. The fourth counter controls the number
of integration periods per time slot. See Figure 2 for a block
diagram. Note that the counters are ignored for the
immediate threshold decisions.
The user can program a separate code for output on the
EOUT bus for each of the eight possible states of the three
MSBs of the attenuator control register. These codes can be
up to 8 bits, but if four gain control sections are used, only
four bits are available for each gain control section. The
mapping of the gain control bits to EOUT bits is done in
GWA = 0001h and the codes are programmed in IWA =
0*17h and 0*18h.
The three MSBs of the attenuator control register can be
routed internally to the channels to be used as the floating-
point exponents. This adds gain in 6 dB steps to compensate
for the 6 dB steps of RF attenuator. The MSBs can be added
to the input exponent bits if desired. There is a
programmable delay from the attenuator control register to
the channel input to compensate for RF/IF filter group delay
and A/D and ISL5416 pipeline delays.
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