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参数资料
| 型号： | ISL5416KI |
| 厂商： | INTERSIL CORP |
| 元件分类： | 无绳电话/电话 |
| 英文描述： | Four-Channel Wideband Programmable DownConverter |
| 中文描述： | TELECOM, CELLULAR, BASEBAND CIRCUIT, PBGA256 |
| 封装： | 17 X 17 MM, PLASTIC, BGA-256 |
| 文件页数： | 4/71页 |
| 文件大小： | 2013K |
| 代理商： | ISL5416KI |
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4
Pin Descriptions
NAME
TYPE
INTERNAL
PULL-UP/DOWN
DESCRIPTION
POWER SUPPLY
Vcc
-
Positive Power Supply Voltage (core), 1.8V
±
0.09
VccIO
-
Positive Power Supply Voltage (I/O), 3.3V
±
0.165
GND
-
Ground, 0V.
INPUTS
Ain(16:0)
I
PULL DOWN
Parallel Data Input bus A. Sampled on the rising or falling edge (programmable) of clock when ENIA
is active (low). The bus order can be programmed (See IWA = 0*00h, bit 4).
Bin(16:0)
I
PULL DOWN
Parallel Data Input bus B. Sampled on the rising or falling edge (programmable) of clock when ENIB
is active (low). The bus order can be programmed (See IWA = 0*00h, bit 4).
Cin(16:0)
I
PULL DOWN
Parallel Data Input bus C. Sampled on the rising or falling edge (programmable) of clock when ENIC
is active (low). The bus order can be programmed (See IWA = 0*00h, bit 4).
Din(16:0)
I
PULL DOWN
Parallel Data Input bus D. Sampled on the rising or falling edge (programmable) of clock when ENID
is active (low). The bus order can be programmed (See IWA = 0*00h, bit 4).
ENIA
I
PULL DOWN
Input enable for Parallel Data Input bus A. Active low. This pin enables the input to the part in one of
two modes, gated or interpolated. In gated mode, one sample is taken per CLK when ENIx is
asserted.
ENIB
I
PULL DOWN
Input enable for Parallel Data Input bus B. Active low. This pin enables the input to the part in one of
two modes, gated or interpolated. In gated mode, one sample is taken per CLK when ENIx is
asserted.
ENIC
I
PULL DOWN
Input enable for Parallel Data Input bus C. Active low. This pin enables the input to the part in one of
two modes, gated or interpolated. In gated mode, one sample is taken per CLK when ENIx is
asserted.
ENID
I
PULL DOWN
Input enable for Parallel Data Input bus D. Active low. This pin enables the input to the part in one of
two modes, gated or interpolated. In gated mode, one sample is taken per CLK when ENIx is
asserted.
CONTROL
CLKA
I
PULL DOWN
Input clock for data bus A. CLKA or CLKC may be used for Ain(16:0).
CLKB
I
PULL DOWN
Input clock for data bus B. CLKB or CLKC may be used for Bin(16:0).
CLKC
I
Input clock for data bus C. CLKC is also the master clock for all channels of ISL5416
CLKD
I
PULL DOWN
Input clock for data bus D. CLKD or CLKC may be used for Din(16:0).
SYNCIn1
I
PULL DOWN
Global synchronization input signal 1. SYNCIn1 can update the carrier NCOs, reset decimation
counters, restart the filter, and restart the output section among other functions. For most of the
functional blocks, the response to SYNCIn1 is programmable and can be enabled or disabled.
SYNCIn2
I
PULL DOWN
Global synchronization input signal 2. SYNCIn2 can update the carrier NCOs, reset decimation
counters, restart the filter, and restart the output section among other functions. For most of the
functional blocks, the response to SYNCIn2 is programmable and can be enabled or disabled.
SYNCO
O
Synchronization Output Signal. The processing of multiple ISL5416 devices can be synchronized by
tying the SYNCO from one ISL5416 device (the master) to the SYNCIn of all the ISL5416 devices
(the master and slaves). An optional internal SYNCO to SYNCInX connection is provided.
RESET
I
PULL UP
Reset Signal. Active low. Asserting reset will halt all processing and set certain registers to default
values.
ISL5416
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