参数资料
| 型号： | ISL6227IRZ |
| 厂商： | Intersil |
| 文件页数： | 18/27页 |
| 文件大小： | 0K |
| 描述： | IC CONTROLLER DDR, DDR2 28QFN |
| 标准包装： | 60 |
| 应用： | 控制器，DDR，DDR2 |
| 输入电压： | 5 V ~ 28 V |
| 输出数： | 2 |
| 输出电压： | 0.9 V ~ 5.5 V |
| 工作温度： | -40°C ~ 100°C |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 28-VFQFN 裸露焊盘 |
| 供应商设备封装： | 28-QFN 裸露焊盘（5x5） |
| 包装： | 管件 |
第1页第2页第3页第4页第5页第6页第7页第8页第9页第10页第11页第12页第13页第14页第15页第16页第17页当前第18页第19页第20页第21页第22页第23页第24页第25页第26页第27页
ISL6227
1.25pF
500k
resistor R CS , output LC filter, and voltage feedback network,
the system loop gain can be accurately analyzed and
modified by the system designers based on the application
TO PWM
COMPARATOR
4.4k
1M 15pF
-
+
Vc
0.9V
300k
VSEN
requirements.
60
50
40
LC FILTER
ISEN
30
20
10
VO/VC
COMPENSATOR
FIGURE 38. THE INTERNAL COMPENSATOR
0
Its transfer function can be written as Equation 12:
-10
-20
LOOP GAIN
1.857 ? 10 ? --------------- + 1 ? ? --------------- + 1 ?
? 2 π f ? ? 2 π f ?
Gcomp ( s ) = ---------------------------------------------------------------------------------------------
s ? --------------- + 1 ?
? 2 π f ?
5 s s
z1 z2
s
p1
(EQ.12)
-30
-40
-50
-60
100
1?10 3
1?10 4
1?10 5
1?10 6
FREQUENCY (Hz)
where:
f z1 = 6.98kHz, f z2 = 380kHz, and f p1 = 137kHz
Outside the ISL6227 chip, a capacitor C z can be placed in
parallel with the top resistor in the feedback resistor divider,
as shown in Figure 34. In this case the transfer function from
the output voltage to the middle point of the divider can be
written as Equation 13:
FIGURE 39. THE BODE PLOT OF THE LC FILTER,
COMPENSATOR, CONTROL TO OUTPUT
VOLTAGE TRANSFER FUNCTION, AND SYSTEM
LOOP GAIN
Gate Control Logic
The gate control logic translates generated PWM signals
into gate drive signals providing necessary amplification,
R 2 sR 1 C z + 1
R 1 + R 2 s ( R 1 || R 2 ) C z + 1
Gfd ( s ) = --------------------- ----------------------------------------------
(EQ.13)
level shift, and shoot-through protection. It bears some
functions that help to optimize the IC performance over a
wide range of the operational conditions. As MOSFET
The ratio of R 1 and R 2 is determined by the output voltage
set point; therefore, the position of the pole and zero
frequency in the above equation may not be far apart;
however, they can improve the loop gain and phase margin
with the proper design.
The C z can bring the high frequency transient output voltage
variation directly to the VSEN pin to cause the PGOOD drop.
Such an effect should be considered in the selection of C z .
From the analysis above, the system loop gain can be
written as Equation 14:
switching time can vary dramatically from type to type, and
with the input voltage, the gate control logic provides
adaptive dead time by monitoring real gate waveforms of
both the upper and the lower MOSFETs.
Dual-Step Conversion
The ISL6227 dual channel controller can be used either in
power systems with a single-stage power conversion, when
the battery power is converted into the desired output
voltage in one step, or in the systems where some
intermediate voltages are initially established. The choice of
the approach may be dictated by the overall system design
Gloop ( s ) = G ( s ) ? Gcomp ( s ) ? Gfd ( s )
(EQ.14)
criteria, or the approach may be a matter of voltages
available to the system designer, as in the case of PCI card
Figure 39 shows the composition of the system loop gain. As
shown in the graph, the power stage becomes a well
damped second order system as compared to the LC filter
characteristics. The ESR zero is so close to the high
frequency pole that they cancel each other out. The power
stage behaves like a first order system. With an internal
compensator, the loop gain transfer function has a cross
over frequency at about 30kHz. With a given set of
parameters, including the MOSFET r DS(ON) , current sense
18
applications.
When the output voltage is regulated from low voltage such
as 5V, the feed-forward ramp may become too shallow,
creating the possibility of duty-factor jitter; this is particularly
relevant in a noisy environment. Noise susceptibility, when
operating from low level regulated power sources, can be
improved by connecting the VIN pin to ground, by which the
feed-forward ramp generator will be internally reconnected
from the VIN pin to the VCC pin, and the ramp slew rate will
be doubled.
FN9094.7
May 4, 2009
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相关代理商/技术参数 |
参数描述 |
|---|---|
| ISL6227IRZ-T | 功能描述:IC CONTROLLER DDR, DDR2 28QFN RoHS:是 类别:集成电路 (IC) >> PMIC - 稳压器 - 专用型 系列:- 标准包装:43 系列:- 应用:控制器，Intel VR11 输入电压:5 V ~ 12 V 输出数:1 输出电压:0.5 V ~ 1.6 V 工作温度:-40°C ~ 85°C 安装类型:表面贴装 封装/外壳:48-VFQFN 裸露焊盘 供应商设备封装:48-QFN（7x7） 包装:管件 |
| ISL6228 | 制造商:INTERSIL 制造商全称:Intersil Corporation 功能描述:High-Performance Dual-Output Buck Controller for Notebook Applications |
| ISL6228EVAL3Z | 功能描述:EVALUATION BOARD FOR ISL6228 RoHS:是 类别:编程器，开发系统 >> 评估板 - DC/DC 与 AC/DC（离线）SMPS 系列:Robust Ripple Regulator™ (R³) 产品培训模块:Obsolescence Mitigation Program 标准包装:1 系列:True Shutdown™ 主要目的:DC/DC，步升 输出及类型:1，非隔离 功率 - 输出:- 输出电压:- 电流 - 输出:1A 输入电压:2.5 V ~ 5.5 V 稳压器拓扑结构:升压 频率 - 开关:3MHz 板类型:完全填充 已供物品:板 已用 IC / 零件:MAX8969 |
| ISL6228HIEVAL3Z | 功能描述:EVALUATION BOARD FOR ISL6228HI RoHS:是 类别:编程器，开发系统 >> 评估板 - DC/DC 与 AC/DC（离线）SMPS 系列:Robust Ripple Regulator™ (R³) 产品培训模块:Obsolescence Mitigation Program 标准包装:1 系列:True Shutdown™ 主要目的:DC/DC，步升 输出及类型:1，非隔离 功率 - 输出:- 输出电压:- 电流 - 输出:1A 输入电压:2.5 V ~ 5.5 V 稳压器拓扑结构:升压 频率 - 开关:3MHz 板类型:完全填充 已供物品:板 已用 IC / 零件:MAX8969 |
| ISL6228HRTZ | 功能描述:IC REG CTRLR BUCK PWM 28-TQFN RoHS:是 类别:集成电路 (IC) >> PMIC - 稳压器 - DC DC 切换控制器 系列:Robust Ripple Regulator™ (R³) 产品培训模块:Lead (SnPb) Finish for COTS Obsolescence Mitigation Program 标准包装:2,500 系列:- PWM 型:电流模式 输出数:1 频率 - 最大:275kHz 占空比:50% 电源电压:18 V ~ 110 V 降压:无 升压:无 回扫:无 反相:无 倍增器:无 除法器:无 Cuk:无 隔离:是 工作温度:-40°C ~ 85°C 封装/外壳:8-SOIC（0.154"，3.90mm 宽） 包装:带卷 (TR) |
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