参数资料
| 型号： | ISL6263DHRZ-T |
| 厂商： | Intersil |
| 文件页数： | 16/17页 |
| 文件大小： | 0K |
| 描述： | IC VREG 3BIT 1PHASE 32-QFN |
| 标准包装： | 6,000 |
| 应用： | 转换器，GPU 内核电源 |
| 输入电压： | 5 V ~ 25 V |
| 输出数： | 1 |
| 输出电压： | 0.7 V ~ 1.09 V |
| 工作温度： | -10°C ~ 100°C |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 32-VFQFN 裸露焊盘 |
| 供应商设备封装： | 32-QFN（5x5） |
| 包装： | 带卷 (TR) |
ISL6263D
traces and components. The paddle on the bottom of the
ISL6263D QFN package is not electrically connected to the
IC, however, it is recommended to make a good thermal
connection to the VSS island using several vias. Connect the
input capacitors, the output capacitors and the source of the
lower MOSFETs to the power ground plane.
LGATE, PVCC, and PGND
PGND is the return path for the pull-down of the LGATE
low-side MOSFET gate driver. Ideally, PGND should be
connected to the source of the low-side MOSFET with a
low-resistance, low-inductance path. The LGATE trace should
be routed in parallel with the trace from the PGND pin. These
two traces should be short, wide and away from other traces
because of the high peak current and extremely fast dv/dt.
PVCC should be decoupled to PGND with a ceramic capacitor
physically located as close as practical to the IC pins.
IMON, SOFT, OCSET, VW, COMP, FB, VDIFF,
ICOMP, ISP, ISN and VO
The traces and components associated with these pins
require close proximity to the IC as well as close proximity to
each other. This section of the converter circuit needs to be
located above the island of analog ground with the
single-point connection to the VSS pin.
Resistor R S
Resistor R S is preferably located near the boundary
between the power ground and the island of analog ground
connected to the VSS pin.
VSEN and RTN
These traces should be laid out as noise sensitive. For
optimum load line regulation performance, the traces
connecting these two pins to the Kelvin sense leads of the
VIAS TO
GROUND
PLANE
INDUCTOR
GND
VOUT
PHASE
NODE
OUTPUT
CAPACITORS
SCHOTTKY
DIODE
LOW-SIDE
MOSFETS
processor should be laid out away from rapidly rising voltage
nodes, (switching nodes) and other noisy traces. The filter
capacitors C FILTER1 , C FILTER2 , and C FILTER3 used in
conjunction with filter resistors R FILTER1 and R FILTER2 form
common mode and differential mode filters, as shown in
Figure 5. The noise environment of the application and
actual board layout conditions will drive the extent of filter
VIN
HIGH-SIDE
MOSFETS INPUT
CAPACITORS
FIGURE 10. TYPICAL POWER COMPONENT PLACEMENT
UGATE, BOOT, and PHASE
PHASE is the return path for the entire UGATE high-side
MOSFET gate driver. The layout for these signals require
similar treatment, but to a greater extent, than those for
LGATE, PVCC, and PGND. These signals swing from
approximately VIN to VSS and are more likely to couple into
other signals.
RBIAS
The resistor R RBIAS should be placed in close proximity to
the ISL6263D using a noise-free current return path to the
VSS pin.
VIN
The VIN signal should be connected near the drain of the
high-side MOSFET.
complexity. The maximum recommended resistance for
R FILTER1 and R FILTER2 is approximately 10 ? to avoid
interaction with the 50k ? input resistance of the remote
sense differential amplifier. The physical location of these
resistors is not as critical as the filter capacitors. Typical
capacitance values for C FILTER1 , C FILTER2 , and C FILTER3
range between 330pF to 1000pF and should be placed near
the IC.
VID<0:2>, OFFSET<0:1>, AF_EN, PGOOD, and
VR_ON
These are logic signals that do not require special attention.
FDE
This logic signal should be treated as noise sensitive and
should be routed away from rapidly rising voltage nodes,
(switching nodes) and other noisy traces.
Copper Size for the Phase Node
The parasitic capacitance and parasitic inductance of the
phase node should be kept very low to minimize ringing. It is
best to limit the size of the PHASE node copper in strict
accordance with the current and thermal management of the
application. An MLCC should be connected directly across
the drain of the high-side MOSFET and the source of the
low-side MOSFET to suppress turn-off voltage spikes.
All Intersil U.S. products are manufactured, assembled and tested utilizing ISO9000 quality systems.
Intersil Corporation’s quality certifications can be viewed at www.intersil.com/design/quality
Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time without
notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and
reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result
from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.
For information regarding Intersil Corporation and its products, see www.intersil.com
16
FN6753.1
July 8, 2010
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相关代理商/技术参数 |
参数描述 |
|---|---|
| ISL6263EVAL1 | 制造商:Intersil Corporation 功能描述:ISL6263 EVALUATION BOARD 1 - IMVP LICENSE REQUIRED - Bulk |
| ISL6264 | 制造商:INTERSIL 制造商全称:Intersil Corporation 功能描述:Two-Phase Core Controller for AMD Mobile Turion CPUs |
| ISL6264CRZ | 功能描述:IC CORE CTRLR TWO-PHASE 40-QFN RoHS:是 类别:集成电路 (IC) >> PMIC - 稳压器 - 专用型 系列:- 标准包装:43 系列:- 应用:控制器，Intel VR11 输入电压:5 V ~ 12 V 输出数:1 输出电压:0.5 V ~ 1.6 V 工作温度:-40°C ~ 85°C 安装类型:表面贴装 封装/外壳:48-VFQFN 裸露焊盘 供应商设备封装:48-QFN（7x7） 包装:管件 |
| ISL6264CRZ-T | 功能描述:IC CORE CTRLR TWO-PHASE 40-QFN RoHS:是 类别:集成电路 (IC) >> PMIC - 稳压器 - 专用型 系列:- 标准包装:43 系列:- 应用:控制器，Intel VR11 输入电压:5 V ~ 12 V 输出数:1 输出电压:0.5 V ~ 1.6 V 工作温度:-40°C ~ 85°C 安装类型:表面贴装 封装/外壳:48-VFQFN 裸露焊盘 供应商设备封装:48-QFN（7x7） 包装:管件 |
| ISL6265 | 制造商:INTERSIL 制造商全称:Intersil Corporation 功能描述:Multi-Output Controller with Integrated MOSFET Drivers for AMD SVI Capable |
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