参数资料
| 型号： | ISL6263DHRZ-T |
| 厂商： | Intersil |
| 文件页数： | 9/17页 |
| 文件大小： | 0K |
| 描述： | IC VREG 3BIT 1PHASE 32-QFN |
| 标准包装： | 6,000 |
| 应用： | 转换器，GPU 内核电源 |
| 输入电压： | 5 V ~ 25 V |
| 输出数： | 1 |
| 输出电压： | 0.7 V ~ 1.09 V |
| 工作温度： | -10°C ~ 100°C |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 32-VFQFN 裸露焊盘 |
| 供应商设备封装： | 32-QFN（5x5） |
| 包装： | 带卷 (TR) |
ISL6263D
Theory of Operation
The R 3 Modulator
The heart of the ISL6263D is Intersil’s Robust-Ripple-Regulator
(R 3 ) Technology?. The R 3 modulator is a hybrid of fixed
frequency PWM control, and variable frequency hysteretic
control that will simultaneously affect the PWM switching
within 10% of the VID set-point then counts 13 switching
cycles, then changes the open-drain output of the PGOOD pin
to high impedance. During soft-start, the regulator always
operates in continuous conduction mode (CCM).
VR_ON
frequency and PWM duty cycle in response to input voltage
and output load transients.
The term “Ripple” in the name “Robust-Ripple-Regulator”
refers to the synthesized voltage-ripple signal V R that
appears across the internal ripple-capacitor C R. The V R
signal is a representation of the output inductor ripple
current. Transconductance amplifiers measuring the input
voltage of the converter and the output set-point voltage
V SOFT /V OUT
PGOOD
~100μs
90%
V SOFT , together produce the voltage-ripple signal V R .
A voltage window signal V W is created across the VW and
COMP pins by sourcing a current proportional to g m V SOFT
through a parallel network consisting of resistor R FSET and
capacitor C FSET. The synthesized voltage-ripple signal V R
along with similar companion signals are converted into
PWM pulses.
The PWM frequency is proportional to the difference in
amplitude between V W and V COMP . Operating on these
large-amplitude, low noise synthesized signals allows the
ISL6263D to achieve lower output ripple and lower phase
jitter than either conventional hysteretic or fixed frequency
PWM controllers. Unlike conventional hysteretic converters,
the ISL6263D has an error amplifier that allows the controller
to maintain tight voltage regulation accuracy throughout the
VID range from 0.7V to 1.0875V.
Voltage Programming
The output voltage V OUT is regulated to the SOFT pin
voltage, V SOFT , which is determined by the DAC output and
is programmed by the external three VID pins. Another two
pins OFFSET0 and OFFSET1 incrementally provide
+12.5mV and +25mV offset of the DAC output voltage,
respectively. Table 1 shows the DAC output specification.
Power-On Reset
The ISL6263D is disabled until the voltage at the VDD pin
has increased above the rising VDD power-on reset (POR)
V DD_THR threshold voltage. The controller will become
disabled when the voltage at the VDD pin decreases below
the falling POR V DD_THF threshold voltage.
Start-Up Timing
Figure 4 shows the ISL6263D start-up timing. Once VDD has
ramped above V DD_THR , the controller can be enabled by
pulling the VR_ON pin voltage above the input-high threshold
V VR_ONH . Approximately 100μs later, the soft-start capacitor
C SOFT begins slewing to the designated VID set-point as it is
charged by the soft-start current source I SS . The V OUT output
voltage of the converter follows the V SOFT voltage ramp to
9
13 SWITCHING CYCLES
FIGURE 4. ISL6263D START-UP TIMING
Static Regulation
The V OUT output voltage will be regulated to the value set
by the VID inputs per Table 1. A true differential amplifier
connected to the VSEN and RTN pins implements processor
Kelvin sense for precise core voltage regulation at the GPU
voltage sense points.
The ISL6263D can accommodate DCR current sense or
discrete resistor current sense. The DCR current sense uses
the intrinsic series resistance of the output inductor, as
shown in the application circuit of Figure 2. The discrete
resistor current sense uses a shunt connected in series with
the output inductor, as shown in the application circuit of
Figure 3. In both cases the signal is fed to the non-inverting
input of the current sense amplifier at the ISP pin, where it is
measured differentially with respect to the output voltage of
the converter at the VO pin and amplified. The voltage at the
ICOMP pin minus the output voltage measured at the VO
pin, is proportional to the total inductor current. This
information is used for overcurrent protection and current
monitoring. It is important to note that this current
measurement should not be confused with the synthetic
current ripple information created within the R 3 modulator.
When using inductor DCR current sense, an NTC
compensation network is optional to compensate the
positive temperature coefficient of the copper winding, thus
maintaining the current sense accuracy.
Processor Kelvin Voltage Sense
The remote voltage sense input pins VSEN and RTN of the
ISL6263D are to be terminated at the die of the GPU. Kelvin
sense allows the voltage regulator to tightly control the
processor voltage at the die, compensating for various
resistive voltage drops in the power delivery path.
FN6753.1
July 8, 2010
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| ISL6263EVAL1 | 制造商:Intersil Corporation 功能描述:ISL6263 EVALUATION BOARD 1 - IMVP LICENSE REQUIRED - Bulk |
| ISL6264 | 制造商:INTERSIL 制造商全称:Intersil Corporation 功能描述:Two-Phase Core Controller for AMD Mobile Turion CPUs |
| ISL6264CRZ | 功能描述:IC CORE CTRLR TWO-PHASE 40-QFN RoHS:是 类别:集成电路 (IC) >> PMIC - 稳压器 - 专用型 系列:- 标准包装:43 系列:- 应用:控制器，Intel VR11 输入电压:5 V ~ 12 V 输出数:1 输出电压:0.5 V ~ 1.6 V 工作温度:-40°C ~ 85°C 安装类型:表面贴装 封装/外壳:48-VFQFN 裸露焊盘 供应商设备封装:48-QFN（7x7） 包装:管件 |
| ISL6264CRZ-T | 功能描述:IC CORE CTRLR TWO-PHASE 40-QFN RoHS:是 类别:集成电路 (IC) >> PMIC - 稳压器 - 专用型 系列:- 标准包装:43 系列:- 应用:控制器，Intel VR11 输入电压:5 V ~ 12 V 输出数:1 输出电压:0.5 V ~ 1.6 V 工作温度:-40°C ~ 85°C 安装类型:表面贴装 封装/外壳:48-VFQFN 裸露焊盘 供应商设备封装:48-QFN（7x7） 包装:管件 |
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