参数资料
| 型号： | ISL6264CRZ |
| 厂商： | Intersil |
| 文件页数： | 18/23页 |
| 文件大小： | 0K |
| 描述： | IC CORE CTRLR TWO-PHASE 40-QFN |
| 标准包装： | 50 |
| 应用： | 控制器，AMD 移动式 Turion? |
| 输入电压： | 5 V ~ 24 V |
| 输出数： | 1 |
| 输出电压： | 0.38 V ~ 1.55 V |
| 工作温度： | -10°C ~ 100°C |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 40-VFQFN 裸露焊盘 |
| 供应商设备封装： | 40-QFN（6x6） |
| 包装： | 管件 |
ISL6264
Using a SLEWRATE of 4.2mV/μs, and the typical I 2 value,
given in the Electrical Specification table of 230μA, C SOFT is
shown in Equation 3:
Static Mode of Operation - Processor Die Sensing
Die sensing is the ability of the controller to regulate the core
output voltage at a remotely sensed point. This allows the
C SOFT ≡ ( 230 μ A ) ? ( 4.2 )
(EQ. 3)
voltage regulator to compensate for various resistive drops
in the power path and ensure that the voltage seen at the
A choice of 0.047μF would guarantee a SLEWRATE of
3.7mV/μs is met for minimum I 3 value, given in the
C SOFT will then control the Start-Up slew rate as well. One
should expect the output voltage to slew to the VID value of
1.2V at a rate given by Equation 4:
CPU die is the correct level independent of load current.
The VSEN and RTN pins of the ISL6264 are connected to
Kelvin sense leads at the die of the processor through the
processor socket. These signal names are V CC_SENSE and
V CC_SENSE respectively. This allows the voltage regulator to
tightly control the processor voltage at the die, independent
dV I SS 43 μ A
0.047 μ F
C SOFT
------- = ------------------- = ----------------------- = 0.9
dt
mV
? ( μ S )
(EQ. 4)
of layout inconsistencies and voltage drops. This Kelvin
sense technique provides for extremely tight load line
regulation.
Selecting R BIAS
To properly bias the ISL6264, a reference current is
established by placing a 147k Ω , 1% tolerance resistor from
the RBIAS pin to ground. This will provide a highly accurate,
10A current source from which OCSET reference current
can be derived.
Care should be taken in layout that the resistor is placed
very close to the RBIAS pin and that a good quality signal
ground is connected to the opposite side of the R BIAS
resistor. Do not connect any other components to this pin as
this would negatively impact performance. Capacitance on
this pin would create instabilities and should be avoided.
Start-up Operation - PGOOD
The internal timer allows PGOOD to go high approximately
7.6ms after Vout reaches the target VID voltage during the
start-up.
These traces should be laid out as noise sensitive traces.
For optimum load line regulation performance, the traces
connecting these two pins to the Kelvin sense leads of the
processor must be laid out away from rapidly rising voltage
nodes, (switching nodes) and other noisy traces. To achieve
optimum performance, place common mode and differential
mode capacitor filters to analog ground on VSEN and RTN.
Whether to need these capacitors really depends on the
actual board layout and noise environment.
Due to the fact that the voltage feedback to the switching
regulator is sensed at the processor die, there exists the
potential of an over voltage due to an open circuited
feedback signal, should the regulator be operated without
the processor installed. Due to this fact, we recommend the
use of the Ropn1 and Ropn2 connected to V OUT and ground
(illustrated in Figure 31). These resistors will provide voltage
feedback in the event that the system is powered up without
a processor installed. These resistors may typically range
from 20 Ω to 100 Ω .
ISEN1
ISEN1
ISEN2
ISEN2
OC
10μA
-
+
INTERNAL TO
ISL6264
+
DROOP
-
OCSET
VSUM
DFB
R OCSET
V O'
VSUM
I PHASE1
RS
VSUM
R L1
L 1
C L1
+ VDCR - 1
DCR
RO1
1 -
S
+
+
DROOP
I PHASE2
ISEN1
L 2
VO'
DCR
V OUT
1 -
+
VDIFF
0.018μF
+
RTN
VSEN
0.018μF
10
VO'
R OPN1
TO V OUT
R OCSET
V O'
VSUM
RS
R L2
ISEN2
+
2 -
VDCR
C L2
VO'
RO2
C BULK
ESR
VCC_SENSE
TO PROCESSOR
R OPN2
VSS_SENSE
SOCKET KELVIN
CONNECTIONS
FIGURE 31. SIMPLIFIED SCHEMATIC FOR DROOP AND DIE SENSING WITH INDUCTOR DCR CURRENT SENSING
18
FN6359.3
May 28, 2009
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