参数资料
型号: ISL6264CRZ
厂商: Intersil
文件页数: 20/23页
文件大小: 0K
描述: IC CORE CTRLR TWO-PHASE 40-QFN
标准包装: 50
应用: 控制器,AMD 移动式 Turion?
输入电压: 5 V ~ 24 V
输出数: 1
输出电压: 0.38 V ~ 1.55 V
工作温度: -10°C ~ 100°C
安装类型: 表面贴装
封装/外壳: 40-VFQFN 裸露焊盘
供应商设备封装: 40-QFN(6x6)
包装: 管件
ISL6264
R n ( T ) = -------------------------------------------------------------
( R series + R ntc ) ? R par
R drp2 = ? ------------------------------------- – 1 ? ? 1k Ω = 5.62k Ω
2 ? R droop
? 0.0008 ? 0.769
?
The resultant NTC network resistor value is dependent on
the temperature and given by Equation 7:
(EQ. 7)
R series + R ntc + R par
For simplicity, the gain of V N to the V DCR_EQU is defined by
G1, also dependent on the temperature of the NTC
thermistor (see Equation 8).
Droop Impedance (R DROOP ) = 0.002 (V/A) as per the AMD
specification, DCR = 0.0008 Ω typical for a 0.36μH inductor,
Rdrp1 = 1k Ω and the attenuation gain (G1) = 0.77, Rdrp2 is
then:
(EQ. 16)
Note, we choose to ignore the R O resistors because they do
G 1 ( T ) = ----------------------------------------
R n ( T )
R n ( T ) + R sequ
DCR ( T ) = DCR 25C ? ( 1 + 0.00393*(T-25) )
(EQ. 8)
(EQ. 9)
not add significant error.
These designed values in R n network are very sensitive to
layout and coupling factor of the NTC to the inductor. As only
one NTC is required in this application, this NTC should be
Therefore, the output of the droop amplifier divided by the
total load current can be expressed in Equation 10:
placed as close to the Channel 1 inductor as possible and
PCB traces sensing the inductor voltage should be go
directly to the inductor pads.
R droop = G 1 ( T ) ? ------------------- ? ( 1 + 0.00393*(T-25) ) ? k droop
DCR 25
2
(EQ. 10)
Once the board has been laid out, some adjustments may
be required to adjust the full load droop voltage. This is fairly
easy and can be accomplished by allowing the system to
where R DROOP is the realized load line slope and 0.00393 is
the temperature coefficient of the copper. To achieve the
droop value independent from the temperature of the
inductor, it is equivalently expressed by Equation 11:
achieve thermal equilibrium at full load, and then adjusting
Rdrp2 to obtain the appropriate load line slope.
To see whether the NTC has compensated the temperature
change of the DCR, the user can apply full load current and
k droopamp = 1 + ----------------
G 1 ( T ) ? ( 1 + 0.00393*(T-25) ) ? G 1t arg et
The non-inverting droop amplifier circuit has the gain
k droopamp expressed as shown in Equation 12:
R drp2
R drp1
(EQ. 11)
(EQ. 12)
wait for the thermal steady state and see how much the
output voltage will deviate from the initial voltage reading. A
good compensation can limit the drift to 2mV. If the output
voltage is decreasing with temperature increase, that ratio
between the NTC thermistor value and the rest of the
resistor divider network has to be increased. The user
should follow the evaluation board value and layout of NTC
G 1 ( T ) = -------------------------------------------------------
1 1t arg et
( 1 + 0.00393*(T-25) )
G 1target is the desired gain of Vn over I OUT . DCR/2.
Therefore, the temperature characteristics of gain of Vn is
described in Equation 13:
(EQ. 13)
For the G1 target = 0.76, the R ntc = 10k Ω with b = 4300,
R series = 2610k Ω , and R par = 11k Ω , R seqv = 1825 Ω generates
a desired G1, close to the feature specified in Equation 20.
The actual G1 at +25°C is 0.769. For different G1 and NTC
as much as possible to minimize engineering time.
The 2mV/A load line should be adjusted by Rdrp2 based on
maximum current, not based on small current steps like 10A,
as the droop gain might vary between each 10A steps.
Basically, if the max current is 40A, the required droop
voltage is 84mV. The user should have 40A load current on
and look for 84mV droop. If the drop voltage is less than
84mV, for example, 80mV. the new value will be calculated
by:
R drp2 = ---------------- ( R drp1 + R drp2 ) – R drp1
thermistor preference, the design file to generate the proper
value of R ntc , R series , R par , and R seqv is provided by Intersil.
84mV
80mV
(EQ. 17)
Then, the individual resistors from each phase to the VSUM
node, labeled R S1 and R S2 in Figure 31, are then given by
Equation 14.
Do not let the mismatch get larger than 600 Ω . To reduce the
mismatch, multiply both R drp1 and R drp2 by the appropriate
factor. The appropriate factor in the example is
Rs = 2 ? R seqv
(EQ. 14)
1404/853 = 1.65. In summary, the predicted load line with
the designed droop network parameters based on the
So, R S = 3650 Ω . Once we know the attenuation of the R S and
R n network, we can then determine the droop amplifier gain
required to achieve the load line. Setting Rdrp1 = 1k_1%,
then Rdrp2 is can be found using Equation 15:
design tool is shown in Figure 33.
R drp2 = ? ---------------------------------------------- – 1 ? ? R drp1
2 ? R droop
? DCR ? G1 ( 25 ° C ) ?
20
(EQ. 15)
FN6359.3
May 28, 2009
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