参数资料
| 型号： | ISL6265HRTZ-T |
| 厂商： | Intersil |
| 文件页数： | 11/24页 |
| 文件大小： | 0K |
| 描述： | IC CTLR MULTI-OUTPUT 48-TQFN |
| 标准包装： | 4,000 |
| 应用： | 控制器，AMD SVI 兼容移动式 CPU |
| 输入电压： | 5 V ~ 24 V |
| 输出数： | 3 |
| 输出电压： | 0.5 V ~ 1.55 V |
| 工作温度： | -10°C ~ 100°C |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 48-WFQFN 裸露焊盘 |
| 供应商设备封装： | 48-TQFN-EP（6x6） |
| 包装： | 带卷 (TR) |
ISL6265
output ripple and lower phase jitter than either conventional
hysteretic or fixed frequency PWM controllers. Unlike
.
VIN
conventional hysteretic converters, the ISL6265 has an error
amplifier that allows the controller to maintain a 0.5% voltage
PWM FREQUENCY
CONTROL
FSET
regulation accuracy throughout the VID range from 0.75V to
1.55V. Voltage regulation accuracy is slightly wider, ±5mV,
over the VID range from 0.7375V to 0.5V.
+
g m V IN
+
V W
-
+
R
PWM Q
The hysteresis window voltage is relative to the error
VO
+
V R
S
amplifier output such that load current transients result in
increased switching frequency, which gives the R 3 regulator
a faster response than conventional fixed frequency PWM
controllers. In uniplane configurations, transient load current
g m V O
+
-
V COMP
C R TO
PWM
CONTROL
+
ISL6265
is inherently shared between active phases due to the use of
a common hysteretic window voltage. Individual average
phase currents are monitored and controlled to equally
share current among the active phases.
FIGURE 5. MODULATOR CIRCUITRY
Modulator
RIPPLE CAPACITOR VOLTAGE C R
WINDOW VOLTAGE V W
The ISL6265 modulator features Intersil’s
R 3
technology, a
hybrid of fixed frequency PWM control and variable
frequency hysteretic control (see Figure 5). Intersil’s R 3
technology can simultaneously affect the PWM switching
frequency and PWM duty cycle in response to input voltage
and output load transients. The R 3 modulator synthesizes an
AC signal V R , which is an analog representation of the
output inductor ripple current. The duty-cycle of V R is the
result of charge and discharge current through a ripple
capacitor C R . The current through C R is provided by a
transconductance amplifier g m that measures the VIN and
VO voltages. The positive slope of V R can be written as
determined by Equation 1:
ERROR AMPLIFIER VOLTAGE V COMP
PWM
FIGURE 6. MODULATOR WAVEFORMS DURING LOAD
TRANSIENT
V RPOS = ( g m ) ? ( V IN – V OUT )
(EQ. 1)
Initialization
The negative slope of V R can be written as determined by
Equation 2:
Once sufficient bias is applied to the VCC pin, internal logic
checks the status of critical pins to determine the controller
V RNEG = g m ? V OUT
(EQ. 2)
operation profile prior to ENABLE. These pins include RTN1
which determines single vs two-phase operation and
Where g m is the gain of the transconductance amplifier.
A window voltage V W is referenced with respect to the error
amplifier output voltage V COMP , creating an envelope into
which the ripple voltage V R is compared. The amplitude of
V W is set by a resistor connected across the FSET and GND
pins. The V R, V COMP, and V W signals feed into a window
comparator in which V COMP is the lower threshold voltage
and V W is the higher threshold voltage. Figure 6 shows
PWM pulses being generated as V R traverses the V W and
V COMP thresholds. The PWM switching frequency is
proportional to the slew rates of the positive and negative
slopes of V R; it is inversely proportional to the voltage
between V W and V COMP .
11
OFS/VFIXEN for enabling/disabling the SVI interface and core
voltage droop. Depending on the configuration set by these
pins, the controller then checks the state of the SVC and SVD
pins to determine the soft-start target output voltage level.
Power-On Reset
The ISL6265 requires a +5V input supply tied to VCC and
PVCC to exceed a rising power-on reset (POR) threshold
before the controller has sufficient bias to guarantee proper
operation. Once this threshold is reached or exceeded, the
ISL6265 has enough bias to begin checking RTN1,
OFS/VFIXEN, ENABLE, and SVI inputs. Hysteresis between
the rising the falling thresholds assure the ISL6265 will not
inadvertently turn-off unless the bias voltage drops
substantially (see “Electrical Specifications” on page 8).
Core Configuration
The ISL6265 determines the core channel requirements of
the CPU based on the state of the RTN1 pin prior to
FN6599.1
May 13, 2009
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