参数资料
| 型号： | ISL6265HRTZ-T |
| 厂商： | Intersil |
| 文件页数： | 22/24页 |
| 文件大小： | 0K |
| 描述： | IC CTLR MULTI-OUTPUT 48-TQFN |
| 标准包装： | 4,000 |
| 应用： | 控制器，AMD SVI 兼容移动式 CPU |
| 输入电压： | 5 V ~ 24 V |
| 输出数： | 3 |
| 输出电压： | 0.5 V ~ 1.55 V |
| 工作温度： | -10°C ~ 100°C |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 48-WFQFN 裸露焊盘 |
| 供应商设备封装： | 48-TQFN-EP（6x6） |
| 包装： | 带卷 (TR) |
ISL6265
The bootstrap capacitor must have a maximum voltage
rating above PVCC + 4V and its capacitance value is
selected per Equation 27:
capacitors (ceramic) should be placed as close as possible
to the decoupling target (microprocessor), making use of the
shortest connection paths to any internal planes. Place the
C BOOT ≥ ------------------------
Q g
Δ V BOOT
(EQ. 27)
components in such a way that the area under the IC has
less noise traces with high dV/dt and di/dt, such as gate
signals and phase node signals.
Where:
- Q g is the total gate charge required to turn on the
VIAS TO
GROUND
GND
OUTPUT
high-side MOSFET
- Δ V BOOT , is the maximum allowed voltage decay across
the boot capacitor each time the high-side MOSFET is
PLANE
VOUT
CAPACITORS
SCHOTTKY
DIODE
switched on
As an example, suppose the high-side MOSFET has a total
gate charge Q g , of 25nC at V GS = 5V, and a Δ V BOOT of
200mV. The calculated bootstrap capacitance is 0.125μF; for
INDUCTOR
HIGH-SIDE
MOSFETS
PHASE
NODE
VIN
LOW-SIDE
MOSFETS
INPUT
CAPACITORS
a comfortable margin, select a capacitor that is double the
calculated capacitance. In this example, 0.22μF will suffice.
Use a low temperature-coefficient ceramic capacitor.
PCB Layout Considerations
Power and Signal Layers Placement on the PCB
As a general rule, power layers should be close together,
either on the top or bottom of the board, with the weak
analog or logic signal layers on the opposite side of the
board. The ground-plane layer should be adjacent to the
signal layer to provide shielding. The ground plane layer
should have an island located under the IC, the
compensation components, and the FSET components. The
island should be connected to the rest of the ground plane
FIGURE 13. TYPICAL POWER COMPONENT PLACEMENT
Signal Ground and Power Ground
The bottom of the ISL6265 QFN package is the signal
ground (GND) terminal for analog and logic signals of the IC.
Connect the GND pad of the ISL6265 to the island of ground
plane under the top layer using several vias, for a robust
thermal and electrical conduction path. Connect the input
capacitors, the output capacitors, and the source of the
lower MOSFETs to the power ground plane.
Routing and Connection Details
Specific pins (and the trace routing from them), require extra
attention during the layout process. The following
sub-sections outline concerns by pin name.
layer at one point.
PGND PINS
Component Placement
There are two sets of critical components in a DC/DC
converter; the power components and the small signal
components. The power components are the most critical
because they switch large amount of energy. The small
signal components connect to sensitive nodes or supply
critical bypassing current and signal coupling.
The power components should be placed first and these
include MOSFETs, input and output capacitors, and the
inductor. It is important to have a symmetrical layout for each
power train, preferably with the controller located equidistant
from each power train. Symmetrical layout allows heat to be
dissipated equally across all power trains. Keeping the
distance between the power train and the control IC short
helps keep the gate drive traces short. These drive signals
include the LGATE, UGATE, PGND, PHASE and BOOT.
When placing MOSFETs, try to keep the source of the upper
MOSFETs and the drain of the lower MOSFETs as close as
thermally possible (see Figure 13). Input high-frequency
capacitors should be placed close to the drain of the upper
MOSFETs and the source of the lower MOSFETs. Place the
output inductor and output capacitors between the
MOSFETs and the load. High-frequency output decoupling
22
This is the return path for the pull-down of the LGATE
low-side MOSFET gate driver. Ideally, PGND should be
connected to the source of the low-side MOSFET with a
low-resistance, low-inductance path.
VIN PIN
The VIN pin should be connected close to the drain of the
high-side MOSFET, using a low- resistance and
low-inductance path.
VCC PIN
For best performance, place the decoupling capacitor very
close to the VCC and GND pins.
PVCC PIN
For best performance, place the decoupling capacitor very
close to the PVCC and respective PGND pins, preferably on
the same side of the PCB as the ISL6265 IC.
ENABLE AND PGOOD PINS
These are logic signals that are referenced to the GND pin.
Treat as a typical logic signal.
FN6599.1
May 13, 2009
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