参数资料
| 型号： | ISL6265HRTZ-T |
| 厂商： | Intersil |
| 文件页数： | 19/24页 |
| 文件大小： | 0K |
| 描述： | IC CTLR MULTI-OUTPUT 48-TQFN |
| 标准包装： | 4,000 |
| 应用： | 控制器，AMD SVI 兼容移动式 CPU |
| 输入电压： | 5 V ~ 24 V |
| 输出数： | 3 |
| 输出电压： | 0.5 V ~ 1.55 V |
| 工作温度： | -10°C ~ 100°C |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 48-WFQFN 裸露焊盘 |
| 供应商设备封装： | 48-TQFN-EP（6x6） |
| 包装： | 带卷 (TR) |
ISL6265
The resistor values must also meet the R BIAS requirement
that the total series resistance to ground equal 117k Ω .
CURRENT
SEE FIGURE 9 FOR
SENSE
ADDITIONAL DETAIL
NORTHBRIDGE OC DETECTION
5x
ISP
ISN
+
V c
_
Northbridge OC sensing is achieved via r DS(ON) sensing
across the lower MOSFET. An internal 10μA current source
develops a voltage across R OCSET_NB , which is compared
with the voltage developed across the low-side MOSFET as
5 x V C(OC) @
OC TRIP CURRENT
BIAS
CKT
R BIAS
1.17V
measured at the PHASE pin. When the voltage drop across
the MOSFET exceeds the voltage drop across the resistor,
R OCSETNB = -------------------------------------
OC
-
+
V OCSET
6
6
10μA
OCSET
R BIAS
V OCSET
R OCSET
an OC event occurs. The OCSET_NB resistor is selected
based on the relationship in Equation 16.
I OC ? r DS ( ON )
(EQ. 16)
10 μ A
ISL6265
Where I OC is the OC trip level selected for the Northbridge
FIGURE 10. OC TRIP CIRCUITRY
The sense capacitor voltage, V C , will increase as inductor
current rises per Equation 7. When the inductor current rises
to the OC trip level, the voltage across the sense capacitor
will reach a maximum based on the resistor ratio K. This
maximum value, V C(OC) , is gained up by a factor of 5 and
compared to the static OC trip level set by the OCSET pin.
The recommended voltage range for V C,OC is 6mV to 25mV,
which sets the resistor divider ratio K, where I OC is the user-
defined OC trip level (see Equation 13). Typical inductor
DCR values are on the order of 1m Ω which result in more
than enough voltage drop to support this V C,OC range.
application and r DS(ON) is the drain-source ON-resistance of
the lower MOSFET.
OC FAULT RESPONSE
When an OC fault occurs on any combination of outputs,
both Core and Northbridge regulators shutdown and the
driver outputs are tri-stated. The PGOOD signal transitions
low indicating a fault condition. The controller will not attempt
to restart the regulators and the user must toggle either EN
or VCC to clear the fault condition.
Overvoltage Protection
The ISL6265 monitors the individual Core and Northbridge
output voltages using differential remote sense amplifiers.
V C ( OC )
I OC ? DCR
K = ----------------------------
(EQ. 13)
During an OV, PGOOD is latched low and the upper and
lower MOSFETs are turned off on all outputs. Inductor
The resistor divider components also impact time-constant
matching, these components need to meet the parallel
combination requirements of Equation 9.
Based on the selected V C(OC) level, the required OC monitor
trip level is set. The recommended V C(OC) level range will
result in an OC monitor trip level range of 30mV to 125mV
based on the internal gain of 5.
This OC monitor trip level sets the voltage level required at
the OCSET pin to create an OC fault at the user-defined OC
trip level. A resistor divider from the RBIAS pin to ground
with the mid-point connected to OCSET sets the voltage at
the pin (see Figure 10). This voltage is internally divided by 6
and compared with V C(OC) . Working backwards, the voltage
required at the OCSET pin to achieve this OC trip level
ranges from 180mV to 0.750mV as defined in Equation 14.
current will decay through the MOSFET body diodes. This
condition can be reset by bringing EN low or by bringing
VCC below 3.9V. When these inputs are returned to their
high operating levels, the controller soft-starts.
The ISL6265 features a severe overvoltage (OV) threshold
of 1.8V. If any of the outputs exceed this voltage, an OV fault
is immediately triggered. PGOOD is latched low and the
low-side MOSFETs of the offending output(s) are turned on.
The low-side MOSFETs will remain on until the output
voltage is pulled below 0.85V at which time all MOSFETs are
turned off. If the output again rises above 1.8V, the
protection process repeats. This offers protection against a
shorted high-side MOSFET while preventing output voltage
from ringing below ground. The OV is reset by toggling EN
low. OV detection is active at all times that the controller is
enabled including after one of the other faults occurs so that
V OCSET = V C ( OC ) ? 30
(EQ. 14)
the processor is protected against high-side MOSFET
leakage while the MOSFETs are commanded off.
The resistor divider ratio used to determine the R BIAS and
R OCSET values is shown in Equation 15.
Undervoltage Protection
Undervoltage protection is independent of the OC limit. A
R OCSET V OCSET
R OCSET + R BIAS
------------------------------------------------ = -----------------------
1.17V
19
(EQ. 15)
fault latches if any of the sensed output voltages are less
than the VID set value by a nominal 295mV for 1ms. The
FN6599.1
May 13, 2009
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