参数资料
| 型号： | ISL6265HRTZ-T |
| 厂商： | Intersil |
| 文件页数： | 17/24页 |
| 文件大小： | 0K |
| 描述： | IC CTLR MULTI-OUTPUT 48-TQFN |
| 标准包装： | 4,000 |
| 应用： | 控制器，AMD SVI 兼容移动式 CPU |
| 输入电压： | 5 V ~ 24 V |
| 输出数： | 3 |
| 输出电压： | 0.5 V ~ 1.55 V |
| 工作温度： | -10°C ~ 100°C |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 48-WFQFN 裸露焊盘 |
| 供应商设备封装： | 48-TQFN-EP（6x6） |
| 包装： | 带卷 (TR) |
ISL6265
AMD specifications do not require droop and provide no load
line guidelines. Tight static output voltage tolerance limits
push acceptable level of droop below a useful level for Griffin
applications. Care must be taken in applications which
implement droop to balance time constant mismatch, sense
capacitor resistor ratio, OC trip and droop equations.
Temperature shifts related to DCR must also be addressed,
as outlined in the previous section.
NORTHBRIDGE CURRENT SENSE
During the off-time following a PHASE transition low, the
Northbridge controller samples the voltage across the lower
MOSFET r DS(ON) . A ground-referenced amplifier is
connected to the PHASE node through a resistor,
R OCSET_NB . The voltage across R OCSET_NB is equal to the
voltage drop across the r DS(ON) of the lower MOSFET while
it is conducting. The resulting current into the OCSET_NB
pin is proportional to the inductor current. The sensed
inductor current is used for overcurrent protection and
voltage droop.
Selecting RBIAS For Core Outputs
To properly bias the ISL6265, a reference current is
established by placing a 117k Ω , 1% tolerance resistor from
the RBIAS pin to ground. This will provide a highly accurate,
10μA current source from which OC reference current is
derived.
Care must be taken in layout to place the resistor very close
to the RBIAS pin. A good quality signal ground should be
connected to the opposite end of the R BIAS resistor. Do not
connect any other components to this pin as this would
negatively impact performance. Capacitance on this pin
could create instabilities and is to be avoided.
A resistor divider off this pin is used to set the Core side OC
trip level. Additional direction on how to size is provided in
the resistor divider.
Offset Resistor Selection
If the OFS pin is connected to ground through a resistor, the
ISL6265 operates in SVI mode with droop active. The
resistor between the OFS pin and ground sets the positive
Core voltage offset per Equation 11.
Internal Driver Operation
The ISL6265 features three internal gate-drivers to support
the Core and Northbridge regulators and to reduce solution
size. The drivers include a diode emulation mode, which
helps to improve light-load efficiency.
MOSFET Gate-Drive Outputs
The ISL6265 has internal gate-drivers for the high-side and
low-side N-Channel MOSFETs. The low-side gate-drivers
are optimized for low duty-cycle applications where the
low-side MOSFET conduction losses are dominant,
requiring a low r DS(ON) MOSFET. The LGATE pull-down
resistance is low in order to strongly clamp the gate of the
MOSFET below the V GS(th) at turn-off. The current transient
through the gate at turn-off can be considerable because the
gate charge of a low r DS(ON) MOSFET can be large.
Adaptive shoot-through protection prevents a gate-driver
output from turning on until the opposite gate-driver output
has fallen below approximately 1V.
The high-side gate-driver output voltage is measured across
the UGATE and PHASE pins while the low-side gate-driver
output voltage is measured across the LGATE and PGND
pins. The power for the LGATE gate driver is sourced
directly from the PVCC pin. The power for the UGATE
gate-driver is sourced from a “boot” capacitor connected
across the BOOT and PHASE pins. The boot capacitor is
charged from a 5V bias supply through a “boot diode” each
time the low-side MOSFET turns on, pulling the PHASE pin
low. The ISL6265 has an integrated boot diode connected
from the PVCC pin to the BOOT pin.
Diode Emulation
The ISL6265 implements forced continuous-conduction-
mode (CCM) at heavy load and diode-emulation-mode (DE)
at light load, to optimize efficiency in the entire load range.
The transition is automatically achieved by detecting the
inductor current when PSI_L is low. If PSI_L is high, the
controller disables DE and forces CCM on both Core and NB
regulators.
Positive-going inductor current flows either from the source
of the high-side MOSFET, or out of the drain of the low-side
MOSFET. Negative-going inductor current flows into the
drain of the low-side MOSFET. When the low-side MOSFET
conducts positive inductor current, the phase voltage is
R OFS = ----------------------------
1.2V ? R FB
V OFS
(EQ. 11)
negative with respect to the GND and PGND pins.
Conversely, when the low-side MOSFET conducts negative
inductor current, the phase voltage is positive with respect to
Where V OFS is the user defined output voltage offset.
Typically, V OFS is determined by taking half the total output
voltage droop. The resulting value centers the overall output
voltage waveform around the programmed SVID level. For
example, R FB of 1k Ω and a total output droop of 24mV
would result in an offset voltage of 12mV and a R OFS of
100k Ω .
17
the GND and PGND pins. The ISL6265 monitors the phase
voltage when the low-side MOSFET is conducting inductor
current to determine the direction of the inductor current.
When the output load current is less than half the inductor
ripple current, the inductor current goes negative. Sinking
the negative inductor through the low-side MOSFET lowers
efficiency by preventing DCM period stretching and allowing
FN6599.1
May 13, 2009
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