参数资料
| 型号： | ISL62873HRUZ-T |
| 厂商： | Intersil |
| 文件页数： | 11/17页 |
| 文件大小： | 0K |
| 描述： | IC REG CTRLR BUCK PWM 16UTQFN |
| 标准包装： | 3,000 |
| 系列： | Robust Ripple Regulator™ (R³) |
| PWM 型： | 控制器 |
| 输出数： | 1 |
| 频率 - 最大： | 330kHz |
| 电源电压： | 3.3 V ~ 25 V |
| 降压： | 是 |
| 升压： | 无 |
| 回扫： | 无 |
| 反相： | 无 |
| 倍增器： | 无 |
| 除法器： | 无 |
| Cuk： | 无 |
| 隔离： | 无 |
| 工作温度： | -10°C ~ 100°C |
| 封装/外壳： | 16-UFQFN |
| 包装： | 带卷 (TR) |
ISL62873
C SEN = ------------------------------------------
R OCSET ? DCR
V RPOS = ( g m ) ? ( V IN – V OUT ) ? C R
V RNEG = g m ? V OUT ? C R
correctly not only in DC operation, but also during dynamic
operation, the R-C network time constant R OCSET C SEN
needs to match the inductor time constant L/DCR. The value
of C SEN is then written as Equation 18:
L
(EQ. 18)
For example, if L is 1.5μH, DCR is 4.5m Ω , and R OCSET is
9k Ω, the choice of C SEN = 1.5μH/(9k Ω x 4.5m Ω ) = 0.037μF .
When an OCP fault is declared, the PGOOD pin will
pull-down to 35 Ω and latch off the converter. The fault will
remain latched until the EN pin has been pulled below the
falling EN threshold voltage V ENTHF or if VCC has decayed
below the falling POR threshold voltage VVCC_THF .
Undervoltage
The UVP fault detection circuit triggers after the FB pin
voltage is below the undervoltage threshold V UVTH for more
than 2μs. For example, if the converter is programmed to
regulate 1.0V at the FB pin, that voltage would have to fall
below the typical V UVTH threshold of 84% for more than 2μs
in order to trip the UVP fault latch. In numerical terms, that
would be 84% x 1.0V = 0.84V. When a UVP fault is declared,
the PGOOD pin will pull-down to 95 Ω and latch-off the
converter. The fault will remain latched until the EN pin has
been pulled below the falling EN threshold voltage V ENTHF
or if VCC has decayed below the falling POR threshold
voltage V VCC_THF .
Over-Temperature
When the temperature of the IC increases above the rising
threshold temperature T OTRTH , it will enter the OTP state
that suspends the PWM, forcing the LGATE and UGATE
gate-driver outputs low. The status of the PGOOD pin does
not change nor does the converter latch-off. The PWM
remains suspended until the IC temperature falls below the
hysteresis temperature T OTHYS at which time normal PWM
operation resumes. The OTP state can be reset if the EN pin
is pulled below the falling EN threshold voltage V ENTHF or if
VCC has decayed below the falling POR threshold voltage
and/or reduce the off-time of the PWM pulse in progress.
Conversely, if the application should experience a falling
load transient and/or a rising line transient such that the
output voltage starts to rise, the modulator will truncate the
on-time and/or extend the off-time of the PWM pulse in
progress. The period and duty cycle of the ensuing PWM
pulses are optimized by the R 3 modulator for the remainder
of the transient and work in concert with the error amplifier
V ERR to maintain output voltage regulation. Once the
transient has dissipated and the control loop has recovered,
the PWM frequency returns to the nominal static 300kHz.
Modulator
The R 3 modulator synthesizes an AC signal V R , which is an
analog representation of the output inductor ripple current.
The duty-cycle of V R is the result of charge and discharge
current through a ripple capacitor C R . The current through
C R is provided by a transconductance amplifier g m that
measures the input voltage (V IN ) at the PHASE pin and
output voltage (V OUT ) at the VO pin. The positive slope of
V R can be written as Equation 19:
(EQ. 19)
The negative slope of V R can be written as Equation 20 :
(EQ. 20)
Where, g m is the gain of the transconductance amplifier.
A window voltage V W is referenced with respect to the error
amplifier output voltage V COMP , creating an envelope into
which the ripple voltage V R is compared. The amplitude of
V W is controlled internally by the IC. The V R, V COMP, and
V W signals feed into a window comparator in which V COMP
is the lower threshold voltage and V W is the higher threshold
voltage. Figure 7 shows PWM pulses being generated as V R
traverses the V W and V COMP thresholds. The PWM
switching frequency is proportional to the slew rates of the
positive and negative slopes of V R; it is inversely
proportional to the voltage between V W and V COMP.
VCC_THF . All other protection circuits remain functional
V
while the IC is in the OTP state. It is likely that the IC will
detect an UVP fault because in the absence of PWM, the
output voltage decays below the undervoltage threshold
V UVTH .
Theory of Operation
RIPPLE CAPACITOR VOLTAGE C R
WINDOW VOLTAGE V W
The modulator features Intersil’s R 3 Robust-Ripple-
Regulator technology, a hybrid of fixed frequency PWM
control and variable frequency hysteretic control. The PWM
frequency is maintained at 300kHz under static
continuous-conduction-mode operation within the entire
specified envelope of input voltage, output voltage, and
output load. If the application should experience a rising load
transient and/or a falling line transient such that the output
voltage starts to fall, the modulator will extend the on-time
11
ERROR AMPLIFIER VOLTAGE V COMP
PWM
FIGURE 7. MODULATOR WAVEFORMS DURING LOAD
TRANSIENT
FN6930.1
August 31, 2010
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