参数资料
| 型号： | ISL62873HRUZ-T |
| 厂商： | Intersil |
| 文件页数： | 9/17页 |
| 文件大小： | 0K |
| 描述： | IC REG CTRLR BUCK PWM 16UTQFN |
| 标准包装： | 3,000 |
| 系列： | Robust Ripple Regulator™ (R³) |
| PWM 型： | 控制器 |
| 输出数： | 1 |
| 频率 - 最大： | 330kHz |
| 电源电压： | 3.3 V ~ 25 V |
| 降压： | 是 |
| 升压： | 无 |
| 回扫： | 无 |
| 反相： | 无 |
| 倍增器： | 无 |
| 除法器： | 无 |
| Cuk： | 无 |
| 隔离： | 无 |
| 工作温度： | -10°C ~ 100°C |
| 封装/外壳： | 16-UFQFN |
| 包装： | 带卷 (TR) |
ISL62873
Component Selection for Setpoint Voltage
Programming Resistors
TABLE 1. ISL62873 VID TRUTH TABLE
pin. When SET0 and VCC are tied together, the following
internal reconfigurations take place:
- VID0 pin opens its 500nA pull-down current sink
STATE
VID0
1
CLOSE
SW0
RESULT
V SREF
V SET1
V OUT
V OUT1
- Reference source selector switch SW4 moves from INT
position (internal 500mV) to EXT position (VID0 pin)
- VID1 pin is disabled
The converter will now be in regulation when the voltage on
R SET1 = R SET2 ? ? ----------------------- – 1 ?
? K V SET2 ?
V SET2 = V REF ? ? 1 + ------------------ ?
? R SET1 ?
0 SW1 V SET2 V OUT2
First, determine the attenuation factor K . Next, assign an
initial value to R SET2 of approximately 150k Ω then calculate
R SET1 using Equation 5.
The equation for the value of R SET1 is written as Equation 5:
(EQ. 5)
? V REF ?
The sum of R SET1 and R SET2 programming resistors should
be approximately 300k Ω, as shown in Equation 6, otherwise
adjust the value of R SET2 and repeat the calculations.
R SET1 + R SET2 ? 300k Ω (EQ. 6)
Equations 7 and 8 give the specific V SET gain equations for
the ISL62873 setpoint reference voltages.
The ISL62873 V SET1 setpoint is written as Equation 7:
V SET1 = V REF (EQ. 7)
The ISL62873 V SET2 setpoint is written as Equation 8:
(EQ. 8)
? R SET2 ?
the FB pin equals the voltage on the VID0 pin. As with
resistor-programmed setpoints, the reference voltage range
on the VID0 pin is 500mV to 1.5V. Use Equations 1, 2, and 3
beginning on page 8 should it become necessary to
implement an output voltage-divider network to make the
external setpoint reference voltage compatible with the
500mV to 1.5V constraint.
Soft-Start and Voltage-Step Delay
Circuit Description
When the voltage on the VCC pin has ramped above the
rising power-on reset voltage V VCC_THR , and the voltage on
the EN pin has increased above the rising enable threshold
voltage V ENTHR , the SREF pin releases its discharge clamp
and enables the reference amplifier V SET . The soft-start
current I SS is limited to 20μA and is sourced out of the SREF
pin into the parallel RC network of capacitor C SOFT and
resistance R T . The resistance R T is the sum of all the series
connected R SET programming resistors and is written as
Equation 9:
R T = R SET1 + R SET2 + … R SET ( n ) (EQ. 9)
V OUT
R FB
FB
SREF
?
+
EA
+
V SET
?
SW0
V COMP
V REF
The voltage on the SREF pin rises as I SS charges C SOFT to
the voltage reference setpoint selected by the state of the
VID inputs at the time the EN pin is asserted. The regulator
controls the PWM such that the voltage on the FB pin tracks
the rising voltage on the SREF pin. Once C SOFT charges to
the selected setpoint voltage, the I SS current source comes
out of the 20μA current limit and decays to the static value
set by V SREF ÷ R T . The elapsed time from when the EN pin
is asserted to when V SREF has reached the voltage
reference setpoint is the soft-start delay t SS which is given
by Equation 10:
t SS = – ( R T ? C SOFT ) ? LN ( 1 – ------------------------------ )
SET0
SW1
Where:
V START-UP
I SS ? R T
(EQ. 10)
- I SS is the soft-start current source at the 20μA limit
FIGURE 5. ISL62873 VOLTAGE PROGRAMMING CIRCUIT
External Setpoint Reference
The IC can use an external setpoint reference voltage as an
alternative to VID-selected, resistor-programmed setpoints.
This is accomplished by removing all setpoint programming
resistors, connecting the SET0 pin to the VCC pin, and
feeding the external setpoint reference voltage to the VID0
9
- V START-UP is the setpoint reference voltage selected by
the state of the VID inputs at the time EN is asserted
- R T is the sum of the R SET programming resistors
The end of soft-start is detected by I SS tapering off when
capacitor C SOFT charges to the designated V SET voltage
reference setpoint. The SSOK flag is set, the PGOOD pin
goes high, and the I SS current source changes over to the
voltage-step current source I VS which has a current limit of
±100μA. Whenever the VID inputs or the external setpoint
FN6930.1
August 31, 2010
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相关代理商/技术参数 |
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| ISL62875 | 制造商:INTERSIL 制造商全称:Intersil Corporation 功能描述:PWM DC/DC Controller with VID Inputs for Portable GPU Core-Voltage Regulator |
| ISL62875HRUZ-T | 功能描述:IC REG CTRLR BUCK PWM 20UTQFN RoHS:是 类别:集成电路 (IC) >> PMIC - 稳压器 - DC DC 切换控制器 系列:Robust Ripple Regulator™ (R³) 产品培训模块:Lead (SnPb) Finish for COTS Obsolescence Mitigation Program 标准包装:2,500 系列:- PWM 型:电流模式 输出数:1 频率 - 最大:275kHz 占空比:50% 电源电压:18 V ~ 110 V 降压:无 升压:无 回扫:无 反相:无 倍增器:无 除法器:无 Cuk:无 隔离:是 工作温度:-40°C ~ 85°C 封装/外壳:8-SOIC（0.154"，3.90mm 宽） 包装:带卷 (TR) |
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