参数资料
| 型号： | ISL62873HRUZ-T |
| 厂商： | Intersil |
| 文件页数： | 8/17页 |
| 文件大小： | 0K |
| 描述： | IC REG CTRLR BUCK PWM 16UTQFN |
| 标准包装： | 3,000 |
| 系列： | Robust Ripple Regulator™ (R³) |
| PWM 型： | 控制器 |
| 输出数： | 1 |
| 频率 - 最大： | 330kHz |
| 电源电压： | 3.3 V ~ 25 V |
| 降压： | 是 |
| 升压： | 无 |
| 回扫： | 无 |
| 反相： | 无 |
| 倍增器： | 无 |
| 除法器： | 无 |
| Cuk： | 无 |
| 隔离： | 无 |
| 工作温度： | -10°C ~ 100°C |
| 封装/外壳： | 16-UFQFN |
| 包装： | 带卷 (TR) |
ISL62873
Electrical Specifications
These specifications apply for T A = -10°C to +100°C, unless otherwise stated.
All typical specifications T A = +25°C, VCC = 5V.
MIN
MAX
PARAMETER
SYMBOL
TEST CONDITIONS
(Note 2) TYP (Note 2) UNIT
OCSET Leakage Current
UVP Threshold Voltage
OTP Rising Threshold Temperature (Note 3)
OTP Hysteresis (Note 3)
I OCSET
V UVTH
T OTRTH
T OTHYS
EN = GND
V FB = %V SREF
-
81
-
-
0
84
150
25
-
87
-
-
μA
%
°C
°C
NOTES:
2. Parameters with MIN and/or MAX limits are 100% tested at +25°C, unless otherwise specified. Temperature limits established by characterization
and are not production tested.
3. Limits established by characterization and are not production tested.
V SET ( x ) ? R FB
R OFS = --------------------------------------------
V FB = V OUT ? ----------------------------------
R
+ R
Setpoint Reference Voltage Programming
Voltage identification (VID) pins select user-programmed
setpoint reference voltages that appear at the SREF pin. The
converter is in regulation when the FB pin voltage (V FB )
equals the SREF pin voltage (V SREF .) The IC measures V FB
and V SREF relative to the GND pin, not the PGND pin. The
setpoint reference voltages use the naming convention
V SET(x) where (x) is the first, second, third, or fourth setpoint
reference voltage where:
- V SET1 < V SET2 < V SET3 < V SET4
- V OUT1 < V OUT2 < V OUT3 < V OUT4
The V SET1 setpoint is fixed at 500mV because it
corresponds to the closure of internal switch SW0 that
configures the V SET amplifier as a unity-gain voltage
follower for the 500mV voltage reference V REF .
A feedback voltage-divider network may be required to
achieve the desired reference voltages. Using the feedback
voltage-divider allows the maximum output voltage of the
converter to be higher than the 1.5V maximum setpoint
reference voltage that can be programmed on the SREF pin.
Likewise, the feedback voltage-divider allows the minimum
output voltage of the converter to be higher than the fixed
500mV setpoint reference voltage of V SET1 . Scale the
voltage-divider network such that the voltage V FB equals the
voltage V SREF when the converter output voltage is at the
desired level. The voltage-divider relation is given in
Equation 1:
R OFS
(EQ. 1)
FB OFS
Where:
- K is the attenuation factor
- V SREF( lim ) is the V SREF voltage setpoint of either
500mV or 1.50V
- V OUT( lim ) is the output voltage of the converter when
V SREF = V SREF( lim )
Since the voltage-divider network is in the feedback path, all
output voltage setpoints will be attenuated by K , so it follows
that all of the setpoint reference voltages will be attenuated
by K . It will be necessary then to include the attenuation
factor K in all the calculations for selecting the R SET
programming resistors.
The value of offset resistor R OFS can be calculated only after
the value of loop-compensation resistor R FB has been
determined. The calculation of R OFS is written as Equation 3:
(EQ. 3)
V OUT – V SET ( x )
The setpoint reference voltages are programmed with
resistors that use the naming convention R SET(x) where (x)
is the first, second, third, or fourth programming resistor
connected in series starting at the SREF pin and ending at
the GND pin. When one of the internal switches closes, it
connects the inverting input of the V SET amplifier to a
specific node among the string of R SET programming
resistors. All the resistors between that node and the SREF
pin serve as the feedback impedance R F of the V SET
amplifier. Likewise, all the resistors between that node and
the GND pin serve as the input impedance R IN of the V SET
amplifier. Equation 4 gives the general form of the gain
V SET ( X ) = V REF ? ? 1 + ---------- ?
Where:
- V FB = V SREF
- R FB is the loop-compensation feedback resistor that
connects from the FB pin to the converter output
equation for the V SET amplifier:
? R F ?
? R IN ?
Where:
(EQ. 4)
V SREF ( lim ) R OFS
V OUT ( lim )
R FB + R OFS
- R OFS is the voltage-scaling programming resistor that
connects from the FB pin to the GND pin
The attenuation of the feedback voltage divider is written as:
K = ------------------------------- = ---------------------------------- (EQ. 2)
8
- V REF is the 500mV internal reference of the IC
- V SET(x) is the resulting setpoint reference voltage that
appears at the SREF pin
FN6930.1
August 31, 2010
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