参数资料
| 型号： | ISL62875HRUZ-T |
| 厂商： | Intersil |
| 文件页数： | 16/22页 |
| 文件大小： | 0K |
| 描述： | IC REG CTRLR BUCK PWM 20UTQFN |
| 标准包装： | 3,000 |
| 系列： | Robust Ripple Regulator™ (R³) |
| PWM 型： | 控制器 |
| 输出数： | 1 |
| 频率 - 最大： | 550kHz |
| 电源电压： | 4.75 V ~ 5.25 V |
| 降压： | 是 |
| 升压： | 无 |
| 回扫： | 无 |
| 反相： | 无 |
| 倍增器： | 无 |
| 除法器： | 无 |
| Cuk： | 无 |
| 隔离： | 无 |
| 工作温度： | -10°C ~ 100°C |
| 封装/外壳： | 20-UFQFN |
| 包装： | 带卷 (TR) |
ISL62875
V DCR = I L ? DCR
Figure 9 shows the overcurrent set circuit. The inductor
consists of inductance L and the DC resistance DCR. The
inductor DC current I L creates a voltage drop across
DCR, which is given by Equation 21:
(EQ. 21)
The I OCSET current source sinks 10μA into the OCSET
pin, creating a DC voltage drop across the resistor
R OCSET , which is given by Equation 22:
V ROCSET = 10 μ A ? R OCSET (EQ. 22)
The DC voltage difference between the OCSET pin and
the VO pin, which is given by Equation 23:
V OCSET – V VO = V DCR – V ROCSET = I L ? DCR – I OCSET ? R OCSET
(EQ. 23)
The IC monitors the voltage of the OCSET pin and the VO
pin. When the voltage of the OCSET pin is higher than
the voltage of the VO pin for more than 10μs, an OCP
fault latches the converter off.
Component Selection for R OCSET and C SEN
The value of R OCSET is calculated with Equation 24,
which is written as:
Overvoltage
The ISL62875 does not feature overvoltage fault
protection.
Undervoltage
The UVP fault detection circuit triggers after the FB pin
voltage is below the undervoltage threshold V UVTH for
more than 2μs. For example, if the converter is
programmed to regulate 1.0V at the FB pin, that voltage
would have to fall below the typical V UVTH threshold of
84% for more than 2μs in order to trip the UVP fault
latch. In numerical terms, that would be
84% x 1.0V = 0.84V. When a UVP fault is declared, the
PGOOD pin will pull-down to 95 Ω and latch-off the
converter. The fault will remain latched until the EN pin
has been pulled below the falling EN threshold voltage
V ENTHF or if VCC has decayed below the falling POR
threshold voltage V VCC_THF .
Over-Temperature
When the temperature of the IC increases above the
rising threshold temperature T OTRTH , it will enter the OTP
state that suspends the PWM, forcing the LGATE and
UGATE gate-driver outputs low. The status of the PGOOD
pin does not change nor does the converter latch-off. The
PWM remains suspended until the IC temperature falls
R OCSET = ----------------------------
I OC ? DCR
I OCSET
(EQ. 24)
below the hysteresis temperature T OTHYS at which time
normal PWM operation resumes. The OTP state can be
reset if the EN pin is pulled below the falling EN threshold
(EQ. 25)
C SEN = ------------------------------------------
V O
VCC_THF .
F SW ? L
Where:
- R OCSET ( Ω ) is the resistor used to program the
overcurrent setpoint
- I OC is the output DC load current that will activate
the OCP fault detection circuit
- DCR is the inductor DC resistance
For example, if I OC is 20A and DCR is 4.5m Ω , the choice
of R OCSET is = 20A x 4.5m Ω /10μA = 9k Ω.
Resistor R OCSET and capacitor C SEN form an R-C
network to sense the inductor current. To sense the
inductor current correctly not only in DC operation, but
also during dynamic operation, the R-C network time
constant R OCSET C SEN needs to match the inductor time
constant L/DCR. The value of C SEN is then written as
Equation 25:
L
R OCSET ? DCR
For example, if L is 1.5μH, DCR is 4.5m Ω , and R OCSET is
9k Ω, the choice of C SEN = 1.5μH/(9k Ω x 4.5m Ω ) =
0.037μF .
When an OCP fault is declared, the PGOOD pin will
pull-down to 35 Ω and latch off the converter. The fault
will remain latched until the EN pin has been pulled below
the falling EN threshold voltage V ENTHF or if VCC has
decayed below the falling POR threshold voltage
V
16
voltage V ENTHF or if VCC has decayed below the falling
POR threshold voltage VVCC_THF . All other protection
circuits remain functional while the IC is in the OTP state.
It is likely that the IC will detect an UVP fault because in
the absence of PWM, the output voltage decays below
the undervoltage threshold V UVTH .
General Application Design
Guide
This design guide is intended to provide a high-level
explanation of the steps necessary to design a single-
phase power converter. It is assumed that the reader is
familiar with many of the basic skills and techniques
referenced in the following. In addition to this guide,
Intersil provides complete reference designs that
include schematics, bills of materials, and example
board layouts.
Selecting the LC Output Filter
The duty cycle of an ideal buck converter is a function of
the input and the output voltage. This relationship is
expressed in Equation 26:
D = --------- (EQ. 26)
V IN
The output inductor peak-to-peak ripple current is
expressed in Equation 27:
V O ? ( 1 – D ) (EQ. 27)
I P-P = -------------------------------
September 18, 2009
FN6905.1
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