参数资料
型号: ISL62875HRUZ-T
厂商: Intersil
文件页数: 18/22页
文件大小: 0K
描述: IC REG CTRLR BUCK PWM 20UTQFN
标准包装: 3,000
系列: Robust Ripple Regulator™ (R³)
PWM 型: 控制器
输出数: 1
频率 - 最大: 550kHz
电源电压: 4.75 V ~ 5.25 V
降压:
升压:
回扫:
反相:
倍增器:
除法器:
Cuk:
隔离:
工作温度: -10°C ~ 100°C
封装/外壳: 20-UFQFN
包装: 带卷 (TR)
ISL62875
0.15μF. A good quality ceramic capacitor such as X7R or
X5R is recommended.
source and the voltage spike that occurs when the
MOSFET switches off.
2.0
1.8
1.6
1.4
1.2
1.0
0.8
0.6
0.4
0.2
20nC
Q GATE = 100nC
1000
900
800
700
600
500
400
300
200
100
Q U = 100nC Q U = 50nC
Q L = 200nC Q L = 100nC
Q U = 50nC
Q L = 50nC
Q U = 20nC
Q L = 50nC
0.0
0.0 0.1
0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9
1.0
0
0
200 400 600 800 1k
1.2k 1.4k 1.6k 1.8k 2k
P = F sw ( 1.5V U Q + V L Q ) + P L + P U
(EQ. 35)
P CON_LS ≈ I LOAD ? r DS ( ON ) _LS ? ( 1 – D )
(EQ. 36)
P CON_HS = I LOAD ? r DS ( ON ) _HS ? D
Δ V BOOT_CAP (V)
FIGURE 11. BOOT CAPACITANCE vs BOOT RIPPLE
VOLTAGE
Driver Power Dissipation
Switching power dissipation in the driver is mainly a
function of the switching frequency and total gate charge
of the selected MOSFETs. Calculating the power
dissipation in the driver for a desired application is critical
to ensuring safe operation. Exceeding the maximum
allowable power dissipation level will push the IC beyond
the maximum recommended operating junction
temperature of +125°C. When designing the application,
it is recommended that the following calculation be
performed to ensure safe operation at the desired
frequency for the selected MOSFETs. The power
dissipated by the drivers is approximated as
Equation 34:
(EQ. 34)
U L
Where:
- F sw is the switching frequency of the PWM signal
- V U is the upper gate driver bias supply voltage
FREQUENCY (Hz)
FIGURE 12. POWER DISSIPATION vs FREQUENCY
There are several power MOSFETs readily available that
are optimized for DC/DC converter applications. The
preferred high-side MOSFET emphasizes low switch
charge so that the device spends the least amount of
time dissipating power in the linear region. Unlike the
low-side MOSFET which has the drain-source voltage
clamped by its body diode during turn-off, the high-side
MOSFET turns off with V IN -V OUT , plus the spike, across
it. The preferred low-side MOSFET emphasizes low
r DS(ON) when fully saturated to minimize conduction
loss.
For the low-side MOSFET, (LS), the power loss can be
assumed to be conductive only and is written as
Equation 35:
2
For the high-side MOSFET, (HS), its conduction loss is
written as Equation 36:
2
-
-
V L is the lower gate driver bias supply voltage
Q U is the charge to be delivered by the upper
driver into the gate of the MOSFET and discrete
For the high-side MOSFET, its switching loss is written as
Equation 37:
P SW_HS = ---------------------------------------------------------------------- + ------------------------------------------------------------------
capacitors
- Q L is the charge to be delivered by the lower driver
into the gate of the MOSFET and discrete
capacitors
- P L is the quiescent power consumption of the lower
driver
- P U is the quiescent power consumption of the upper
driver
MOSFET Selection and Considerations
Typically, a MOSFET cannot tolerate even brief excursions
beyond their maximum drain to source voltage rating.
The MOSFETs used in the power stage of the converter
should have a maximum V DS rating that exceeds the
sum of the upper voltage tolerance of the input power
18
V IN ? I VALLEY ? t ON ? F SW V IN ? I PEAK ? t OFF ? F SW
2 2
(EQ. 37)
Where:
- I VALLEY is the difference of the DC component of
the inductor current minus 1/2 of the inductor
ripple current
- I PEAK is the sum of the DC component of the
inductor current plus 1/2 of the inductor ripple
current
- t ON is the time required to drive the device into
saturation
September 18, 2009
FN6905.1
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