参数资料
型号: ISL62883IRTZ
厂商: Intersil
文件页数: 11/37页
文件大小: 0K
描述: IC REG PWM 3PHASE BUCK 40TQFN
标准包装: 60
应用: 控制器,Intel IMVP-6.5?
输入电压: 5 V ~ 21 V
输出数: 1
输出电压: 0.013 V ~ 1.5 V
工作温度: -40°C ~ 100°C
安装类型: 表面贴装
封装/外壳: 40-WFQFN 裸露焊盘
供应商设备封装: 40-TQFN-EP(5x5)
包装: 管件
ISL62883, ISL62883B
Theory of Operation
Multiphase R 3 ? Modulator
VW
VW
MASTER CLOCK CIRCUIT
MASTER
COMP
MASTER
CLOCK
COMP
Vcrm
CLOCK
Phase
Sequencer
Clock1
Clock2
Clock3
Vcrm
gmVo
Crm
Master
VW
Vcrs1
SLAVE CIRCUIT 1
Clock1 S PWM1 Phase1
Q
R
gm
L1
I L1
Vo
Co
Clock
Clock1
PWM1
Clock2
PWM2
Crs1
Clock3
VW
SLAVE CIRCUIT 2
Clock2 S PWM2 Phase2
Q
R
L2
I L2
PWM3
VW
Crs2
Vcrs2
gm
Crs3
VW
Vcrs3
SLAVE CIRCUIT 3
Clock3 S PWM3 Phase3
Q
R
gm
L3
I L3
Vcrs1
Vcrs3
Vcrs2
FIGURE 5. R 3 ? MODULATOROPERATION PRINCIPLES IN LOAD
INSERTION RESPONSE
The ISL62883 is a multiphase regulator, which implements Intel?
IMVP-6.5? protocol. It can be programmed for 1-, 2- or 3-phase
VW
FIGURE 3. R 3 ? MODULATORCIRCUIT
operation for microprocessor core applications. It uses Intersil
patented R 3 ? (Robust Ripple Regulator?) modulator. The R 3 ?
modulator combines the best features of fixed frequency PWM
and hysteretic PWM while eliminating many of their shortcomings.
Figure 3 conceptually shows the ISL62883 multiphase R 3 ?
Vcrm
COMP
Master
Clock
Clock1
PW M1
Clock2
PW M2
Clock3
PW M3
VW
Hysteretic
W indow
modulator circuit, and Figure 4 shows the operation principles.
A current source flows from the VW pin to the COMP pin, creating
a voltage window set by the resistor between the two pins. This
voltage window is called VW window in the following discussion.
Inside the IC, the modulator uses the master clock circuit to
generate the clocks for the slave circuits. The modulator
discharges the ripple capacitor C rm with a current source equal
to g m V o , where g m is a gain factor. C rm voltage V crm is a
sawtooth waveform traversing between the VW and COMP
voltages. It resets to VW when it hits COMP, and generates a one-
shot master clock signal. A phase sequencer distributes the
master clock signal to the slave circuits. If the ISL62883 is in
3-phase mode, the master clock signal will be distributed to the
three phases, and the Clock1~3 signals will be 120° out-of-
phase. If the ISL62883 is in 2-phase mode, the master clock
signal will be distributed to Phases 1 and 2, and the Clock1 and
Clock2 signals will be 180° out-of-phase. If the ISL62883 is in
1-phase mode, the master clock signal will be distributed to
Phases 1 only and be the Clock1 signal.
Vcrs2 Vcrs3 Vcrs1
FIGURE 4. R 3 ? MODULATOR OPERATION PRINCIPLES IN
STEADY STATE
11
Each slave circuit has its own ripple capacitor C rs , whose voltage
mimics the inductor ripple current. A g m amplifier converts the
inductor voltage into a current source to charge and discharge
C rs . The slave circuit turns on its PWM pulse upon receiving the
clock signal, and the current source charges C rs . When C rs
FN6891.4
June 21, 2011
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