参数资料
型号: ISL62883IRTZ
厂商: Intersil
文件页数: 20/37页
文件大小: 0K
描述: IC REG PWM 3PHASE BUCK 40TQFN
标准包装: 60
应用: 控制器,Intel IMVP-6.5?
输入电压: 5 V ~ 21 V
输出数: 1
输出电压: 0.013 V ~ 1.5 V
工作温度: -40°C ~ 100°C
安装类型: 表面贴装
封装/外壳: 40-WFQFN 裸露焊盘
供应商设备封装: 40-TQFN-EP(5x5)
包装: 管件
ISL62883, ISL62883B
ω L = ------------
ω sns = ------------------------------------------------------
R ntcnet × --------------
----------------------------------------- × C n
DCR
L
1
R sum
N
N
R sum
R ntcnet + --------------
(EQ. 22)
(EQ. 23)
i o
Vo
Transfer function A cs (s) always has unity gain at DC. The inductor
DCR value increases as the winding temperature increases,
giving higher reading of the inductor DC current. The NTC R ntc
values decreases as its temperature decreases. Proper
selections of R sum , R ntcs , R p and R ntc parameters ensure that
V Cn represent the inductor total DC current over the temperature
range of interest.
There are many sets of parameters that can properly temperature-
compensate the DCR change. Since the NTC network and the R sum
resistors form a voltage divider, V cn is always a fraction of the
inductor DCR voltage. It is recommended to have a higher ratio of
V cn to the inductor DCR voltage, so the droop circuit has higher
signal level to work with.
A typical set of parameters that provide good temperature
compensation are: R sum = 3.65k Ω , R p = 11k Ω , R ntcs = 2.61k Ω
and R ntc = 10k Ω (ERT-J1VR103J). The NTC network parameters
may need to be fine tuned on actual boards. One can apply full
load DC current and record the output voltage reading
immediately; then record the output voltage reading again when
the board has reached the thermal steady state. A good NTC
network can limit the output voltage drift to within 2mV. It is
recommended to follow the Intersil evaluation board layout and
current-sensing network parameters to minimize engineering
time.
V Cn (s) also needs to represent real-time I o (s) for the controller to
achieve good transient response. Transfer function A cs (s) has a
pole ω sns and a zero ω L . One needs to match ω L and ω sns so
A cs (s) is unity gain at all frequencies. By forcing ω L equal to ω sns
and solving for the solution, Equation 24 solves for the value of
Cn .
FIGURE 16. LOAD TRANSIENT RESPONSE WHEN C n IS TOO
SMALL
i o
Vo
FIGURE 17. LOAD TRANSIENT RESPONSE WHEN C n IS TOO
LARGE
For example, given N = 3, R sum = 3.65k Ω , R p = 11k Ω ,
R ntcs = 2.61k Ω , R ntc = 10k Ω , DCR = 0.88m Ω and L = 0.36μH,
Equation 24 gives C n = 0.406μF.
Assuming the compensator design is correct, Figure 15 shows the
expected load transient response waveforms if C n is correctly
selected. When the load current I core has a square change, the
output voltage V core also has a square response.
If C n value is too large or too small, V Cn (s) will not accurately
represent real-time I o (s) and will worsen the transient response.
Figure 16 shows the load transient response when C n is too
small. V core will sag excessively upon load insertion and may
create a system failure. Figure 17 shows the transient response
when C n is too large. V core is sluggish in drooping to its final
value. There will be excessive overshoot if load insertion occurs
during this time, which may potentially hurt the CPU reliability.
C n = ------------------------------------------------------------
R ntcnet × --------------
----------------------------------------- × DCR
L
R sum
N
N
R sum
R ntcnet + --------------
i o
(EQ. 24)
i o
RING
i L
Vo
BACK
Vo
FIGURE 15. DESIRED LOAD TRANSIENT RESPONSE
WAVEFORMS
20
FIGURE 18. OUTPUT VOLTAGE RING BACK PROBLEM
FN6891.4
June 21, 2011
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