参数资料
型号: ISL62883IRTZ
厂商: Intersil
文件页数: 21/37页
文件大小: 0K
描述: IC REG PWM 3PHASE BUCK 40TQFN
标准包装: 60
应用: 控制器,Intel IMVP-6.5?
输入电压: 5 V ~ 21 V
输出数: 1
输出电压: 0.013 V ~ 1.5 V
工作温度: -40°C ~ 100°C
安装类型: 表面贴装
封装/外壳: 40-WFQFN 裸露焊盘
供应商设备封装: 40-TQFN-EP(5x5)
包装: 管件
ISL62883, ISL62883B
ISUM+
Resistor Current-Sensing Network
Phase1 Phase2 Phase3
Rntcs
Cn.1
L
L
L
Rp
Cn.2 Vcn
Rntc
Rn
OPTIONAL
Ri
ISUM-
DCR
DCR
DCR
Rsum
Rsum
Rsum
ISUM+
Rip
Cip
Rsen
Rsen
Rsen
Ro
Vcn
Cn
Ri
ISUM-
V Cn ( s ) = ------------ × I o ( s ) × A Rsen ( s )
R sen
N
A Rsen ( s ) = ----------------------
s
ω sns
ω Rsen = ---------------------------
R sum
V Cn = ? ----------------------------------------- × ------------ ? × I o
R sum
N
? ?
OPTIONAL
FIGURE 19. OPTIONAL CIRCUITS FOR RING BACK REDUCTION
Figure 18 shows the output voltage ring back problem during
load transient response. The load current i o has a fast step
change, but the inductor current i L cannot accurately follow.
Instead, i L responds in first order system fashion due to the
nature of current loop. The ESR and ESL effect of the output
capacitors makes the output voltage V o dip quickly upon load
current change. However, the controller regulates V o according to
the droop current i droop , which is a real-time representation of i L ;
therefore it pulls V o back to the level dictated by i L , causing the
ring back problem. This phenomenon is not observed when the
output capacitor have very low ESR and ESL, such as all ceramic
capacitors.
Figure 19 shows two optional circuits for reduction of the ring
back. R ip and C ip form an R-C branch in parallel with R i , providing
a lower impedance path than R i at the beginning of i o change.
R ip and C ip do not have any effect at steady state. Through
proper selection of R ip and C ip values, i droop can resemble i o
rather than i L , and V o will not ring back. The recommended value
for R ip is100 Ω . C ip should be determined through tuning the load
transient response waveforms on an actual board. The
recommended range for C ip is 100pF~2000pF.
C n is the capacitor used to match the inductor time constant. It
usually takes the parallel of two (or more) capacitors to get the
desired value. Figure 19 shows that two capacitors C n.1 and C n.2
are in parallel. Resistor R n is an optional component to reduce
the V o ring back. At steady state, C n.1 +C n.2 provides the desired
C n capacitance. At the beginning of i o change, the effective
capacitance is less because R n increases the impedance of the
C n.1 branch. As explained in Figure 16, V o tends to dip when C n is
too small, and this effect will reduce the V o ring back. This effect
is more pronounced when C n.1 is much larger than C n.2 . It is also
more pronounced when R n is bigger. However, the presence of
R n increases the ripple of the V n signal if C n.2 is too small. It is
recommended to keep C n.2 greater than 2200pF. R n value
usually is a few ohms. C n.1 , C n.2 and R n values should be
determined through tuning the load transient response
waveforms on an actual board.
21
Ro
Ro
Io
FIGURE 20. RESISTOR CURRENT-SENSING NETWORK
Figure 20 shows the resistor current-sensing network for a
3-phase solution. Each inductor has a series current-sensing
resistor R sen . R sum and R o are connected to the R sen pads to
accurately capture the inductor current information. The R sum
and R o resistors are connected to capacitor C n . R sum and C n
form a a filter for noise attenuation. Equations 25 thru 27 give
V Cn (s) expression:
(EQ. 25)
1
(EQ. 26)
1 + ------------
1
(EQ. 27)
N
-------------- × C n
Transfer function A Rsen (s) always has unity gain at DC.
Current-sensing resistor R sen value will not have significant
variation over temperature, so there is no need for the NTC
network.
The recommended values are R sum = 1k Ω and C n = 5600pF.
Overcurrent Protection
Refer to Equation 1 and Figures 9, 14 and 20; resistor R i sets the
droop current I droop . Table 3 shows the internal OCP threshold. It
is recommended to design I droop without using the R comp
resistor.
For example, the OCP threshold is 60μA for 3-phase solution. We
will design I droop to be 38.8μA at full load, so the OCP trip level is
1.55 times of the full load current.
For inductor DCR sensing, Equation 28 gives the DC relationship
of V cn (s) and I o (s).
? ?
? R ntcnet DCR ?
(EQ. 28)
N
? R ntcnet + -------------- ?
FN6891.4
June 21, 2011
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