参数资料
| 型号： | ISL6313IRZ |
| 厂商： | Intersil |
| 文件页数： | 17/33页 |
| 文件大小： | 0K |
| 描述： | IC CTRLR PWM 2PHASE BUCK 36-QFN |
| 产品培训模块： | Solutions for Industrial Control Applications |
| 标准包装： | 50 |
| 应用： | 控制器，Intel VR11，AMD CPU |
| 输入电压： | 5 V ~ 12 V |
| 输出数： | 1 |
| 输出电压： | 0.5 V ~ 1.6 V |
| 工作温度： | -40°C ~ 85°C |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 36-WFQFN 裸露焊盘 |
| 供应商设备封装： | 36-TQFN 裸露焊盘（6x6） |
| 包装： | 管件 |
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ISL6313
TABLE 4. AMD 6-BIT VOLTAGE IDENTIFICATION
CODES (Continued)
Voltage Regulation
The integrating compensation network shown in Figure 7
VID5
0
0
0
0
0
0
1
1
1
1
1
VID4
1
1
1
1
1
1
0
0
0
0
0
VID3
1
1
1
1
1
1
0
0
0
0
0
VID2
0
0
1
1
1
1
0
0
0
0
1
VID1
1
1
0
0
1
1
0
0
1
1
0
VID0
0
1
0
1
0
1
0
1
0
1
0
VDAC
0.9000
0.8750
0.8500
0.8250
0.8000
0.7750
0.7625
0.7500
0.7375
0.7250
0.7125
insures that the steady-state error in the output voltage is
limited only to the error in the reference voltage (output of
the DAC) and offset errors in the OFS current source,
remote-sense and error amplifiers. Intersil specifies the
guaranteed tolerance of the ISL6313 to include the
combined tolerances of each of these elements.
The output of the error amplifier, V COMP , is used by the
modulator to generate the PWM signals. The PWM signals
control the timing of the Internal MOSFET drivers and
regulate the converter output so that the voltage at FB is
equal to the voltage at REF. This will regulate the output
voltage to be equal to Equation 8. The internal and external
circuitry that controls voltage regulation is illustrated in
Figure 7.
1
0
0
1
0
1
0.7000
V OUT = V REF – V OFS – V DROOP
(EQ. 8)
1
1
1
1
1
1
0
0
0
0
0
0
0
0
1
1
1
1
1
1
0
0
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0.6875
0.6750
0.6625
0.6500
0.6375
0.6250
The ISL6313 incorporates differential remote-sense
amplification in the feedback path. The differential sensing
removes the voltage error encountered when measuring the
output voltage relative to the controller ground reference
point resulting in a more accurate means of sensing output
voltage.
1
1
1
1
0
0
0
0
1
1
1
1
1
1
1
1
0
0
1
1
0
1
0
1
0.6125
0.6000
0.5875
0.5750
C C
EXTERNAL CIRCUIT
COMP
ISL6313 INTERNAL CIRCUIT
I AVG
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
0
0
1
1
0
1
0
1
0.5625
0.5500
0.5375
0.5250
R C
FB
REF
I OFS
-
+
ERROR
V COMP
1
1
1
1
0
0
1
1
0
0
0
1
0.5125
0.5000
+
C REF
2k
AMPLIFIER
1
1
1
1
0
0
1
1
1
1
0
1
0.4875
0.4750
R FB
(V DROOP + V OFS )
-
VSEN
∑
+
VID
DAC
1
1
1
1
1
1
1
1
1
0
0
0
0
0
1
0
1
0
0.4625
0.4500
0.4375
+
V OUT
-
RGND
+
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
1
1
1
1
1
0
0
1
1
1
0
1
0
1
0.4250
0.4125
0.4000
0.3875
0.3750
FIGURE 7. OUTPUT VOLTAGE AND LOAD-LINE
REGULATION WITH OFFSET ADJUSTMENT
Load-Line (Droop) Regulation
Some microprocessor manufacturers require a
precisely-controlled output resistance. This dependence of
output voltage on load current is often termed “droop” or
“load line” regulation. By adding a well controlled output
impedance, the output voltage can effectively be level shifted
in a direction which works to achieve the load-line regulation
required by these manufacturers.
17
FN6448.2
September 2, 2008
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