参数资料
| 型号： | ISL6313IRZ |
| 厂商： | Intersil |
| 文件页数： | 19/33页 |
| 文件大小： | 0K |
| 描述： | IC CTRLR PWM 2PHASE BUCK 36-QFN |
| 产品培训模块： | Solutions for Industrial Control Applications |
| 标准包装： | 50 |
| 应用： | 控制器，Intel VR11，AMD CPU |
| 输入电压： | 5 V ~ 12 V |
| 输出数： | 1 |
| 输出电压： | 0.5 V ~ 1.6 V |
| 工作温度： | -40°C ~ 85°C |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 36-WFQFN 裸露焊盘 |
| 供应商设备封装： | 36-TQFN 裸露焊盘（6x6） |
| 包装： | 管件 |
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ISL6313
Dynamic VID
Modern microprocessors need to make changes to their core
voltage as part of normal operation. They direct the ISL6313
to do this by making changes to the VID inputs. The ISL6313
is required to monitor the DAC inputs and respond to
on-the-fly VID changes in a controlled manner, supervising a
safe output voltage transition without discontinuity or
disruption. The DAC mode the ISL6313 is operating in,
determines how the controller responds to a dynamic VID
change.
INTEL DYNAMIC VID TRANSITIONS
Compensating Dynamic VID Transitions
During a VID transition, the resulting change in voltage on
the FB pin and the COMP pin causes an AC current to flow
through the error amplifier compensation components from
the FB to the COMP pin. This current then flows through the
feedback resistor, R FB , and can cause the output voltage to
overshoot or undershoot at the end of the VID transition. In
order to ensure the smooth transition of the output voltage
during a VID change, a VID-on-the-fly compensation
network is required. This network is composed of a resistor
and capacitor in series, R DVC and C DVC , between the DVC
and the FB pin.
When in Intel VR11 mode the ISL6313 checks the VID inputs
on the positive edge of an internal 5.5MHz clock. If a new
VSEN
R FB
I DVC = I C
code is established and it remains stable for 3 consecutive
readings (0.36μs to 0.54μs), the ISL6313 recognizes the new
code and changes the internal DAC reference directly to the
I DVC
C C
I C
R C
new level. The Intel processor controls the VID transitions and
C DVC
R DVC
is responsible for incrementing or decrementing one VID step
DVC
FB
COMP
at a time. In VR11 mode, the ISL6313 will immediately change
the internal DAC reference to the new requested value as
soon as the request is validated, which means the fastest
recommended rate at which a bit change can occur is once
REF
x2
-
+
ERROR
every 1μs. If the VID code is changed by more then one step
at a time, the DAC will try to track it at a 5.5MHz step rate.
This will likely cause an overcurrent or overvoltage fault.
C REF
V DAC + R GND
AMPLIFIER
ISL6313 INTERNAL CIRCUIT
t DVID = -------------------------- ? ? --------------------- ?
1 Δ V VID
3 ? 0.00625 ?
AMD DYNAMIC VID TRANSITIONS
When running in AMD 5-bit or 6-bit modes of operation, the
ISL6313 responds differently to a dynamic VID change then
when in Intel VR11 mode. In the AMD modes the ISL6313 still
checks the VID inputs on the positive edge of an internal
5.5MHz clock. In these modes the VID code can be changed
by more than a 1-bit step at a time. If a new code is
established and it remains stable for 3 consecutive readings
(0.36μs to 0.54μs), the ISL6313 recognizes the change and
begins slewing the DAC in 6.25mV steps at a stepping
frequency of 345kHz until the VID and DAC are equal. Thus,
the total time required for a VID change, t DVID , is dependent
only on the size of the VID change ( Δ V VID ).
The time required for a ISL6313-based converter in AMD 5-bit
DAC configuration to make a 1.1V to 1.5V reference voltage
change is about 186μs, as calculated using Equation 14.
(EQ. 14)
345 × 10
VID “OFF” DAC CODES
Both the Intel VR11 and the AMD 5-bit VID tables include “Off”
DAC codes, which indicate to the controller to disable all
FIGURE 10. DYNAMIC VID COMPENSATION NETWORK
This VID-on-the-fly compensation network works by
sourcing AC current into the FB node to offset the effects of
the AC current flowing from the FB to the COMP pin during a
VID transition. To create this compensation current the
ISL6313 sets the voltage on the DVC pin to be 2x the voltage
on the REF pin. Since the error amplifier forces the voltage
on the FB pin and the REF pin to be equal, the resulting
voltage across the series RC between DVC and FB is equal
to the REF pin voltage. The RC compensation components,
R DVC and C DVC , can then be selected to create the desired
amount of compensation current.
The amount of compensation current required is dependant
on the modulator gain of the system, K1, and the error
amplifier R-C components, R C and C C , that are in series
between the FB and COMP pins. Use Equations 15, 16, and
17 to calculate the RC component values, R DVC and C DVC ,
for the VID-on-the-fly compensation network. For these
equations: V IN is the input voltage for the power train; V P-P
is the oscillator ramp amplitude (1.5V); and R C and C C are
the error amplifier R-C components between the FB and
COMP pins.
V IN
A = -----------------
C DVC = --------
regulation. Recognition of these codes is slightly different in that
they must be stable for 4 consecutive readings of a 5.5MHz
clock (0.54μs to 0.72μs) to be recognized. Once an “Off” code
is recognized the ISL6313 latches off, and must be reset by
dropping the EN pin.
19
K1 = ------------
V P-P
R DVC = A × R C
C C
A
K1
K1 – 1
(EQ. 15)
(EQ. 16)
(EQ. 17)
FN6448.2
September 2, 2008
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