参数资料
型号: ISL6313IRZ
厂商: Intersil
文件页数: 9/33页
文件大小: 0K
描述: IC CTRLR PWM 2PHASE BUCK 36-QFN
产品培训模块: Solutions for Industrial Control Applications
标准包装: 50
应用: 控制器,Intel VR11,AMD CPU
输入电压: 5 V ~ 12 V
输出数: 1
输出电压: 0.5 V ~ 1.6 V
工作温度: -40°C ~ 85°C
安装类型: 表面贴装
封装/外壳: 36-WFQFN 裸露焊盘
供应商设备封装: 36-TQFN 裸露焊盘(6x6)
包装: 管件
ISL6313
Functional Pin Description
VCC
VCC is the bias supply for the ICs small-signal circuitry.
Connect this pin to a +5V supply and decouple using a
quality 0.1μF ceramic capacitor.
PVCC
This pin is the power supply pin for the channel MOSFET
drivers, and can be connected to any voltage from +5V to
+12V depending on the desired MOSFET gate-drive level.
Decouple this pin with a quality 1.0μF ceramic capacitor.
GND
GND is the bias and reference ground for the IC.
EN
This pin is a threshold-sensitive (approximately 0.85V) enable
input for the controller. Held low, this pin disables controller
operation. Pulled high, the pin enables the controller for
operation.
FS
A resistor, R S , tied to this pin sets the channel switching
frequency of the controller. Refer to Equation 47 for proper
resistor calculation.
The FS pin also controls whether the internal I AVG current is
connected to the FB pin or not. Tying the R S resistor to
ground connects the I AVG current internally to the FB pin,
allowing the converter to incorporate output voltage droop
proportional to the output current. Tying the R S resistor to
VCC, disconnects the I AVG current internally from the FB
pin.
VID0, VID1, VID2, VID3, VID4, VID5, VID6, and VID7
These are the inputs for the internal DAC that provides the
reference voltage for output regulation. These pins respond to
TTL logic thresholds. These pins are internally pulled high, to
approximately 1.2V, by 40μA internal current sources for Intel
modes of operation, and pulled low by 20μA internal current
sources for AMD modes of operation. The internal pull-up
current decreases to 0 as the VID voltage approaches the
internal pull-up voltage. All VID pins are compatible with
external pull-up voltages not exceeding the IC’s bias voltage
(VCC).
VSEN
This pin senses the microprocessor’s CORE voltage. Connect
this pin to the CORE voltage sense pin or point of the
microprocessor.
RGND
This pin senses the local ground voltage of the
microprocessor and offsets the internal DAC by this sensed
voltage. Connect this pin to the Ground sense pin or point of
the microprocessor.
9
FB and COMP
These pins are the internal error amplifier inverting input and
output respectively. The FB pin, COMP pin, and the VSEN
pins are tied together through external R-C networks to
compensate the regulator.
DVC
A series resistor and capacitor can be connected from the
DVC pin to the FB pin to compensate and smooth dynamic
VID transitions.
IOUT
The IOUT pin is the average channel-current sense output.
This pin is used as a load current indicator to monitor what
the output load current is.
This pin can also be used to set the overcurrent protection
trip level if it desired that a lower level be used then the
internal trip point. Connecting this pin through a resistor to
ground allows the controller to set the alternate overcurrent
protection trip level.
APA
This is the Adaptive Phase Alignment set pin. A 100μA
current flows into the APA pin and by tying a resistor from
this pin to COMP the trip level for the Adaptive Phase
Alignment circuitry can be set.
REF
The REF input pin is the positive input of the error amplifier. It
is internally connected to the DAC output through a 2k Ω
resistor. A capacitor is used between the REF pin and ground
to smooth the voltage transition during soft-start and Dynamic
VID transitions. This pin can also be bypassed to RGND if
desired.
RSET
Connect this pin to VCC through a resistor to set the effective
value of the internal R ISEN current sense resistors. It is
recommended a 0.1μF ceramic capacitor be placed in
parallel with this resistor for noise immunization .
OFS
The OFS pin provides a means to program a dc current for
generating an offset voltage across the resistor between FB
and VSEN. The offset current is generated via an external
resistor and precision internal voltage references. The polarity
of the offset is selected by connecting the resistor to GND or
VCC. For no offset, the OFS pin should be left unconnected.
ISEN1-, ISEN1+, ISEN2-, and ISEN2+
These pins are used for differentially sensing the
corresponding channel output currents. The sensed currents
are used for channel balancing, protection, and load line
regulation.
Connect ISEN1- and ISEN2- to the node between the RC
sense elements surrounding the inductor of their respective
FN6448.2
September 2, 2008
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