参数资料
| 型号： | ISL6313IRZ |
| 厂商： | Intersil |
| 文件页数： | 25/33页 |
| 文件大小： | 0K |
| 描述： | IC CTRLR PWM 2PHASE BUCK 36-QFN |
| 产品培训模块： | Solutions for Industrial Control Applications |
| 标准包装： | 50 |
| 应用： | 控制器，Intel VR11，AMD CPU |
| 输入电压： | 5 V ~ 12 V |
| 输出数： | 1 |
| 输出电压： | 0.5 V ~ 1.6 V |
| 工作温度： | -40°C ~ 85°C |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 36-WFQFN 裸露焊盘 |
| 供应商设备封装： | 36-TQFN 裸露焊盘（6x6） |
| 包装： | 管件 |
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ISL6313
lower-MOSFET body diode. This term is dependent on the
diode forward voltage at I M , V D(ON) , the switching frequency,
f S , and the length of dead times, t d1 and t d2 , at the beginning
and the end of the lower-MOSFET conduction interval
respectively.
The total power dissipated by the upper MOSFET at full load
can now be approximated as the summation of the results
from Equations 27, 28, 29 and 30. Since the power
equations depend on MOSFET parameters, choosing the
correct MOSFETs can be an iterative process involving
? ? ------ + I ----------- ? ? t
? I ?
? I
?
+ ? ------ – ----------- ? ? t
M
P-P
2 ? ?
? N
P
LOW ( 2 )
= V
D ( ON )
? f
S
M P-P
? N 2 ?
d1
?
I
d2
repetitive solutions to the loss equations for different
MOSFETs and different switching frequencies.
(EQ. 26)
The total maximum power dissipated in each lower MOSFET
is approximated by the summation of P LOW(1) and P LOW(2) .
UPPER MOSFET POWER CALCULATION
In addition to r DS(ON) losses, a large portion of the
upper-MOSFET losses are due to currents conducted across
the input voltage (V IN ) during switching. Since a substantially
higher portion of the upper-MOSFET losses are dependent on
switching frequency, the power calculation is more complex.
Upper MOSFET losses can be divided into separate
components involving the upper-MOSFET switching times,
the lower-MOSFET body-diode reverse-recovery charge, Q rr ,
and the upper MOSFET r DS(ON) conduction loss.
When the upper MOSFET turns off, the lower MOSFET does
not conduct any portion of the inductor current until the
voltage at the phase node falls below ground. Once the
lower MOSFET begins conducting, the current in the upper
MOSFET falls to zero as the current in the lower MOSFET
ramps up to assume the full inductor current. In Equation 27,
the required time for this commutation is t 1 and the
approximated associated power loss is P UP(1). .
Package Power Dissipation
When choosing MOSFETs it is important to consider the
amount of power being dissipated in the integrated drivers
located in the controller. Since there are a total of three
drivers in the controller package, the total power dissipated
by all three drivers must be less than the maximum
allowable power dissipation for the QFN package.
Calculating the power dissipation in the drivers for a desired
application is critical to ensure safe operation. Exceeding the
maximum allowable power dissipation level will push the IC
beyond the maximum recommended operating junction
temperature of +125°C. The maximum allowable IC power
dissipation for the 6x6 QFN package is approximately 3.5W
When designing the ISL6313 into an application, it is
recommended that the following calculation is used to ensure
safe operation at the desired frequency for the selected
MOSFETs. The total gate drive power losses, P Qg_TOT , due to
the gate charge of MOSFETs and the integrated driver’s
internal circuitry and their corresponding average driver current
can be estimated with Equations 31 and 32, respectively.
I P-P
I M
P UP ( 1 ) ≈ V IN ? ? ------ + ---------- ? ? ? ---- 1 ? ? f S
? N 2 ? ? 2 ?
? t ?
(EQ. 27)
P Qg_TOT = P Qg_Q1 + P Qg_Q2 + I Q ? VCC
(EQ. 31)
P Qg_Q1 = --- ? Q G1 ? PVCC ? F SW ? N Q1 ? N PHASE
At turn on, the upper MOSFET begins to conduct and this
transition occurs over a time t 2 . In Equation 28, the
3
2
P UP ( 2 ) ≈ V IN ? ? ------ – ---------- ? ? ? ---- 2 ? ? f S
approximate power loss is P UP(2). .
? I M I P-P ? ? t ?
? N 2 ? ? 2 ?
(EQ. 28)
P Qg_Q2 = Q G2 ? PVCC ? F SW ? N Q2 ? N PHASE
(EQ. 32)
I DR = ? --- ? Q G1 ? N
A third component involves the lower MOSFET
reverse-recovery charge, Q rr . Since the inductor current has
3
? 2
Q1
?
+ Q G2 ? N Q2 ? ? N PHASE ? F SW + I Q
fully commutated to the upper MOSFET before the
lower-MOSFET body diode can recover all of Q rr , it is
conducted through the upper MOSFET across VIN. The
power dissipated as a result is P UP(3) .
In Equations 31 and 32, P Qg_Q1 is the total upper gate drive
power loss and P Qg_Q2 is the total lower gate drive power
loss; the gate charge (Q G1 and Q G2 ) is defined at the
particular gate to source drive voltage PVCC in the
P UP ( 3 ) = V IN ? Q rr ? f S
(EQ. 29)
corresponding MOSFET data sheet; I Q is the driver total
quiescent current with no load at both drive outputs; N Q1 and
Finally, the resistive part of the upper MOSFET is given in
Equation 30 as P UP(4). .
N Q2 are the number of upper and lower MOSFETs per phase,
respectively; N PHASE is the number of active phases. The
I Q* VCC product is the quiescent power of the controller
I P-P2
? I M ?
P UP ( 4 ) ≈ r DS ( ON ) ? d ? ? ------ ? + ----------
? N ? 12
2
25
(EQ. 30)
without capacitive load and is typically 75mW at 300kHz.
FN6448.2
September 2, 2008
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相关代理商/技术参数 |
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| ISL6313IRZ-T | 功能描述:IC CTRLR PWM 2PHASE BUCK 36-QFN RoHS:是 类别:集成电路 (IC) >> PMIC - 稳压器 - 专用型 系列:- 标准包装:43 系列:- 应用:控制器，Intel VR11 输入电压:5 V ~ 12 V 输出数:1 输出电压:0.5 V ~ 1.6 V 工作温度:-40°C ~ 85°C 安装类型:表面贴装 封装/外壳:48-VFQFN 裸露焊盘 供应商设备封装:48-QFN（7x7） 包装:管件 |
| ISL6314CRZ | 功能描述:电压模式 PWM 控制器 1-PH PWM CNTRLR W/1 INTEGRTD DRVRS 32LD RoHS:否 制造商:Texas Instruments 输出端数量:1 拓扑结构:Buck 输出电压:34 V 输出电流: 开关频率: 工作电源电压:4.5 V to 5.5 V 电源电流:600 uA 最大工作温度:+ 125 C 最小工作温度:- 40 C 封装 / 箱体:WSON-8 封装:Reel |
| ISL6314CRZ-T | 功能描述:IC CTRLR PWM 1PHASE BUCK 32-QFN RoHS:是 类别:集成电路 (IC) >> PMIC - 稳压器 - 专用型 系列:- 标准包装:43 系列:- 应用:控制器，Intel VR11 输入电压:5 V ~ 12 V 输出数:1 输出电压:0.5 V ~ 1.6 V 工作温度:-40°C ~ 85°C 安装类型:表面贴装 封装/外壳:48-VFQFN 裸露焊盘 供应商设备封装:48-QFN（7x7） 包装:管件 |
| ISL6314CRZ-TR5453 | 制造商:Intersil Corporation 功能描述:STD. ISL6314CRZ-T W/GOLD BOND WIRE ONLY T&R - Tape and Reel |
| ISL6314CRZ-TS2568 | 制造商:Intersil Corporation 功能描述:- Tape and Reel |
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