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参数资料
| 型号： | ISL6316CRZ-T |
| 厂商： | Intersil |
| 文件页数： | 19/29页 |
| 文件大小： | 0K |
| 描述： | IC REG CTRLR BUCK PWM VM 40-QFN |
| 标准包装： | 4,000 |
| PWM 型： | 电压模式 |
| 输出数： | 1 |
| 频率 - 最大： | 275kHz |
| 占空比： | 66.7% |
| 电源电压： | 4.75 V ~ 5.25 V |
| 降压： | 是 |
| 升压： | 无 |
| 回扫： | 无 |
| 反相： | 无 |
| 倍增器： | 无 |
| 除法器： | 无 |
| Cuk： | 无 |
| 隔离： | 无 |
| 工作温度： | 0°C ~ 70°C |
| 封装/外壳： | 40-VFQFN 裸露焊盘 |
| 包装： | 带卷 (TR) |
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ISL6316
PGOOD
VOUT, 500mV/DIV
-
100μA
UV
OC
+
I 1
TD1
TD2
EN_VTT
TD3
50%
DAC
DELAY
SOFT-START, FAULT
AND CONTROL LOGIC
REPEAT FOR
EACH CHANNEL
-
OC
+
100μA
I AVG
PGOOD
500μs/DIV
FIGURE 11. SOFT-START WAVEFORMS
After the DAC voltage reaches the final VID setting, PGOOD
VDIFF
+
-
OV
will be set to high with the fixed delay TD3. The typical value
for TD3 is 85μs.
VID + 0.175V
Fault Monitoring and Protection
The ISL6316 actively monitors output voltage and current to
detect fault conditions. Fault monitors trigger protective
measures to prevent damage to a microprocessor load. One
common power good indicator is provided for linking to
external system monitors. The schematic in Figure 12 outlines
the interaction between the fault monitors and the PGOOD
signal.
PGOOD Signal
The PGOOD pin is an open-drain logic output to indicate that
the soft-start period has completed and the output voltage is
within the regulated range. PGOOD is pulled low during
shutdown and releases high after a successful soft-start and a
fixed delay TD5. PGOOD will be pulled low when an
undervoltage or overvoltage condition is detected, or the
controller is disabled by a reset from EN_PWR, EN_VTT,
POR, or VID OFF-code.
Undervoltage Detection
The undervoltage threshold is set at 60% of the VID code.
When the output voltage at VSEN is below the undervoltage
threshold, PGOOD is pulled low.
19
FIGURE 12. POWER GOOD AND PROTECTION CIRCUITRY
Overvoltage Protection
Regardless of the VR being enabled or not, the ISL6316
overvoltage protection (OVP) circuit will be active after its
POR. The OVP thresholds are different under different
operation conditions. When VR is not enabled and before the
second soft-start, the OVP threshold is 1.275V. Once the
controller detects valid VID input, the OVP trip point will be
changed to VID plus 175mV.
Two actions are taken by the ISL6316 to protect the
microprocessor load when an overvoltage condition occurs.
At the inception of an overvoltage event, all PWM outputs are
commanded low instantly (less than 20ns) until the voltage at
VDIFF falls below 0.4V. This causes the Intersil drivers to turn
on the lower MOSFETs and pull the output voltage below a
level that might cause damage to the load. The PWM outputs
remain low until VDIFF falls below 0.4V, and then PWM
signals enter a high-impedance state. The Intersil drivers
respond to the high-impedance input by turning off both upper
and lower MOSFETs. If the overvoltage condition reoccurs,
the ISL6316 will again command the lower MOSFETs to turn
on. The ISL6316 will continue to protect the load in this
fashion as long as the overvoltage condition occurs.
Once an overvoltage condition is detected, normal PWM
operation ceases until the ISL6316 is reset. Cycling the
voltage on EN_PWR, EN_VTT or VCC below the POR-falling
threshold will reset the controller. Cycling the VID codes will
not reset the controller.
FN9227.1
December 12, 2006
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