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参数资料
| 型号： | ISL6316CRZ-T |
| 厂商： | Intersil |
| 文件页数： | 23/29页 |
| 文件大小： | 0K |
| 描述： | IC REG CTRLR BUCK PWM VM 40-QFN |
| 标准包装： | 4,000 |
| PWM 型： | 电压模式 |
| 输出数： | 1 |
| 频率 - 最大： | 275kHz |
| 占空比： | 66.7% |
| 电源电压： | 4.75 V ~ 5.25 V |
| 降压： | 是 |
| 升压： | 无 |
| 回扫： | 无 |
| 反相： | 无 |
| 倍增器： | 无 |
| 除法器： | 无 |
| Cuk： | 无 |
| 隔离： | 无 |
| 工作温度： | 0°C ~ 70°C |
| 封装/外壳： | 40-VFQFN 裸露焊盘 |
| 包装： | 带卷 (TR) |
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ISL6316
close to the power stage and used to form R FB . Due to the
non-linear temperature characteristics of the NTC, a resistor
network is needed to make the equivalent resistance between
FB and VDIFF pin is reverse proportional to the temperature.
The external temperature compensation network can only
compensate the temperature impact on the droop, while it has
no impact to the sensed current inside ISL6316. Therefore
this network cannot compensate for the temperature impact
LOWER MOSFET POWER CALCULATION
The calculation for heat dissipated in the lower MOSFET is
simple, since virtually all of the heat loss in the lower MOSFET
is due to current conducted through the channel resistance
(r DS(ON) ). In Equation 22, I M is the maximum continuous
output current; I P-P is the peak-to-peak inductor current (see
Equation 1); d is the duty cycle (V OUT /V IN ); and L is the per-
channel inductance.
? I M ? 2 I L , P-P ( 1 – d )
P LOW , 1 = r DS ( ON ) ? ------ ? ( 1 – d ) + -----------------------------------
on the overcurrent protection function.
Current Sense Output
? N ? 12
(EQ. 22)
The current from IDROOP pin is the sensed average current
inside ISL6316. In typical application, IDROOP pin is
connected to FB pin for the application where load line is
required. When load line function is not needed, IDROOP pin
can used to obtain the load current information: with one
resistor from IDROOP pin to GND, the voltage at IDROOP pin
will be proportional to the load current. The resistor from
IDROOP to GND should be chosen to ensure that the voltage
An additional term can be added to the lower-MOSFET loss
equation to account for additional loss accrued during the
dead time when inductor current is flowing through the lower-
MOSFET body diode. This term is dependent on the diode
forward voltage at I M , V D(ON) ; the switching frequency, f S ;
and the length of dead times, t d1 and t d2 , at the beginning and
the end of the lower-MOSFET conduction interval
respectively.
P LOW , 2 = V D ( ON ) f S ? ------ + I ----------- ? t
I P-P ?
d1 + ? ------ – ----------- ? t d2
at IDROOP pin is less than 2V under the maximum load
current.
I M P-P
? N 2 ?
? I
M
? N 2 ?
(EQ. 23)
General Design Guide
This design guide is intended to provide a high-level
explanation of the steps necessary to create a multiphase
power converter. It is assumed that the reader is familiar with
many of the basic skills and techniques referenced below. In
addition to this guide, Intersil provides complete reference
designs that include schematics, bills of materials, and example
board layouts for all common microprocessor applications.
Power Stages
The first step in designing a multiphase converter is to
determine the number of phases. This determination depends
heavily on the cost analysis which in turn depends on system
constraints that differ from one design to the next. Principally,
the designer will be concerned with whether components can
be mounted on both sides of the circuit board; whether through-
hole components are permitted; and the total board space
available for power-supply circuitry. Generally speaking, the
most economical solutions are those in which each phase
handles between 15 and 20A. All surface-mount designs will
tend toward the lower end of this current range. If through-hole
Thus the total maximum power dissipated in each lower
MOSFET is approximated by the summation of P LOW,1 and
P LOW,2 .
UPPER MOSFET POWER CALCULATION
In addition to r DS(ON) losses, a large portion of the upper-
MOSFET losses are due to currents conducted across the
input voltage (V IN ) during switching. Since a substantially
higher portion of the upper-MOSFET losses are dependent on
switching frequency, the power calculation is more complex.
Upper MOSFET losses can be divided into separate
components involving the upper-MOSFET switching times;
the lower-MOSFET body-diode reverse-recovery charge, Q rr ;
and the upper MOSFET r DS(ON) conduction loss.
When the upper MOSFET turns off, the lower MOSFET does
not conduct any portion of the inductor current until the
voltage at the phase node falls below ground. Once the lower
MOSFET begins conducting, the current in the upper
MOSFET falls to zero as the current in the lower MOSFET
ramps up to assume the full inductor current. In Equation 24,
P UP , 1 ≈ V IN ? ------ + ----------- ? ? ---- 1 ? f S
MOSFETs and inductors can be used, higher per-phase
currents are possible. In cases where board space is the
limiting constraint, current can be pushed as high as 40A per
phase, but these designs require heat sinks and forced air to
cool the MOSFETs, inductors and heat-dissipating surfaces.
the required time for this commutation is t 1 and the
approximated associated power loss is P UP,1 .
I M I P-P ? t ?
? N 2 ? ? 2 ?
(EQ. 24)
MOSFETS
The choice of MOSFETs depends on the current each
MOSFET will be required to conduct; the switching frequency;
At turn on, the upper MOSFET begins to conduct and this
transition occurs over a time t 2 . In Equation 25, the
approximate power loss is P UP,2 .
P UP , 2 ≈ V IN ? ------ – ----------- ? ? ---- 2 ? f S
the capability of the MOSFETs to dissipate heat; and the
availability and nature of heat sinking and air flow.
23
? I M I P-P ? ? t ?
? N 2 ? ? 2 ?
(EQ. 25)
FN9227.1
December 12, 2006
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