参数资料
| 型号： | ISL6324ACRZ-T |
| 厂商： | Intersil |
| 文件页数： | 19/40页 |
| 文件大小： | 0K |
| 描述： | IC HYBRID CTRLR PWM DUAL 48QFN |
| 标准包装： | 4,000 |
| 应用： | 控制器，AMD SVI |
| 输入电压： | 5 V ~ 12 V |
| 输出数： | 2 |
| 输出电压： | 最高 2V |
| 工作温度： | 0°C ~ 70°C |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 48-VFQFN 裸露焊盘 |
| 供应商设备封装： | 48-QFN（7x7） |
| 包装： | 带卷 (TR) |
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ISL6324A
POWER SAVINGS MODE: PSI_L
Bit 7 of the Serial VID code transmitted as part of the 8-bit
data phase over the SVI bus is allocated for the PSI_L. If
Bit 7 is 0, then the processor is at an optimal load for the
regulator to enter power savings mode. If Bit 7 is 1, then the
regulator should not be in power savings mode.
With the ISL6324A, Power Savings mode is realized through
phase shedding. Once a Serial VID command with Bit 7 set
to 0 is received, the ISL6324A will shed phases in a
sequential manner. The default number of phases that the
ISL6324A will run on in Power Savings Mode is two. This
number is programmable through the I 2 C interface and can
Voltage Regulation
The integrating compensation network shown in Figure 8
insures that the steady-state error in the output voltage is
limited only to the error in the reference voltage,
remote-sense and error amplifiers. Intersil specifies the
guaranteed tolerance of the ISL6324A to include the
combined tolerances of each of these elements.
The output of the error amplifier, V COMP , is used by the
modulator to generate the PWM signals. The PWM signals
control the timing of the Internal MOSFET drivers and
regulate the converter output so that the voltage at FB is equal
to the voltage at REF. This will regulate the output voltage to
be equal to Equation 11. The internal and external circuitry
that controls voltage regulation is illustrated in Figure 8.
starting with Channel 4. When a phase is shed, that phase
will not go into a tri-state mode until that phase would have
V OUT = V REF – V DROOP
(EQ. 11)
had its PWM go HIGH.
After a phase is shed, the ISL6324A will wait, by default,
1 full PWM cycle before shedding the next phase. This delay
can be changed to 0, 2 or 4 PWM cycle delays through the
I 2 C interface (See “I2C Bus Interface” on page 24). It should
be noted that with a 0 cycle delay, all phases that are to be
The ISL6324A incorporates differential remote-sense
amplification in the feedback path. The differential sensing
removes the voltage error encountered when measuring the
output voltage relative to the controller ground reference point
resulting in a more accurate means of sensing output voltage.
shed will be turned off at the same time. While the option to
shed all phases at once is available, it is not recommended
EXTERNAL CIRCUIT
FS
ISL6324A INTERNAL CIRCUIT
as the Core voltage could be subjected to large output
deviations during the transition.
When leaving Power Savings Mode, through the reception of
R FS
COMP
DROOP
CONTROL
TO
OSCILLATOR
a Serial VID command with Bit 7 set to 1, the ISL6324A will
sequentially turn on phases starting with the lowest
numbered phase that has been shed. When a phase is
being reactivated, it will not leave a tri-state until the PWM of
that phase goes HIGH.
C C
R C
I AVG
After a phase is reactivated, the ISL6324A will wait, by
default, 1 full PWM cycle before reactivating the next phase.
This delay can be changed to 0, 2 or 4 PWM cycle delays
page 24). It should be noted that with a 0 cycle delay, all
phases that have been shed will be turned on at the same
R FB
+
V DROOP
-
FB
-
+
V COMP
ERROR
AMPLIFIER
time. While the option to reactivate all phases at once is
available, it is not recommended as the Core voltage could
be subjected to large output deviations during the transition.
+
VSEN
∑
+
+
VID
DAC
V OUT
If, while in Power Savings Mode, a Serial VID command is
received that forces a VID level change while maintaining
-
RGND
Bit 7 at 0, the ISL632A will first exit the Power Savings Mode
state as previously described. The output voltage will then
be stepped up or down to the appropriate VID level. Finally,
the ISL6324A will then re-enter Power Savings Mode.
If the Core regulator has had an offset voltage added to the
DAC through the I 2 C interface, this offset will, by default,
remain while in Power Savings Mode. Through the I 2 C
interface, the offset can be disabled while in Power Savings
Mode (See “I2C Bus Interface” on page 24).
19
FIGURE 8. OUTPUT VOLTAGE AND LOAD-LINE
REGULATION
Load-Line (Droop) Regulation
By adding a well controlled output impedance, the output
voltage can effectively be level shifted in a direction which
works to achieve a cost-effective solution can help to reduce
the output-voltage spike that results from fast load-current
demand changes.
FN6880.2
May 14, 2010
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相关代理商/技术参数 |
参数描述 |
|---|---|
| ISL6324ACRZ-TR5381 | 制造商:Intersil Corporation 功能描述:4+1 PHASE CONT., CORE + NORTHBRIDGE, PROG PSI, 3.4MHZ SVI, 5 - Tape and Reel 制造商:Intersil Corporation 功能描述:IC HYBRID CTRLR PWM DUAL 48QFN |
| ISL6324AIRZ | 功能描述:IC HYBRID CTRLR PWM DUAL 48QFN RoHS:是 类别:集成电路 (IC) >> PMIC - 稳压器 - 专用型 系列:- 标准包装:43 系列:- 应用:控制器，Intel VR11 输入电压:5 V ~ 12 V 输出数:1 输出电压:0.5 V ~ 1.6 V 工作温度:-40°C ~ 85°C 安装类型:表面贴装 封装/外壳:48-VFQFN 裸露焊盘 供应商设备封装:48-QFN（7x7） 包装:管件 |
| ISL6324AIRZR5381 | 制造商:Intersil Corporation 功能描述:4+1 PHASE CONTROLLER, CORE + NORTHBRIDGE, PROG PSI, 3.4MHZ S - Rail/Tube 制造商:Intersil Corporation 功能描述:IC HYBRID CTRLR PWM DUAL 48QFN |
| ISL6324AIRZ-T | 功能描述:IC HYBRID CTRLR PWM DUAL 48QFN RoHS:是 类别:集成电路 (IC) >> PMIC - 稳压器 - 专用型 系列:- 标准包装:43 系列:- 应用:控制器，Intel VR11 输入电压:5 V ~ 12 V 输出数:1 输出电压:0.5 V ~ 1.6 V 工作温度:-40°C ~ 85°C 安装类型:表面贴装 封装/外壳:48-VFQFN 裸露焊盘 供应商设备封装:48-QFN（7x7） 包装:管件 |
| ISL6324AIRZ-TR5381 | 制造商:Intersil Corporation 功能描述:4+1 PHASE CONTROLLER, CORE + NORTHBRIDGE, PROG PSI, 3.4MHZ S - Tape and Reel 制造商:Intersil Corporation 功能描述:IC HYBRID CTRLR PWM DUAL 48QFN |
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