参数资料
| 型号： | ISL6324ACRZ-T |
| 厂商： | Intersil |
| 文件页数： | 23/40页 |
| 文件大小： | 0K |
| 描述： | IC HYBRID CTRLR PWM DUAL 48QFN |
| 标准包装： | 4,000 |
| 应用： | 控制器，AMD SVI |
| 输入电压： | 5 V ~ 12 V |
| 输出数： | 2 |
| 输出电压： | 最高 2V |
| 工作温度： | 0°C ~ 70°C |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 48-VFQFN 裸露焊盘 |
| 供应商设备封装： | 48-QFN（7x7） |
| 包装： | 带卷 (TR) |
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ISL6324A
Overvoltage Protection
The ISL6324A constantly monitors the sensed output voltage
-
OCL
+
17.5μA
I 1
on the VSEN pin to detect if an overvoltage event occurs.
When the output voltage rises above the OVP trip level and
exceeds the VDDPWRGD OV limit actions are taken by the
12.5μA
-
OCP
REPEAT FOR EACH
CORE CHANNEL
ISL6324A to protect the microprocessor load.
I NB
NB ONLY
+
-
OCP
+
12.5μA
I AVG
CORE ONLY
At the inception of an overvoltage event, both on-board
lower gate pins are commanded low as are the active PWM
outputs to the external drivers, the VDDPWRGD signal is
driven low, and the ISL6324A latches off normal PWM
action. This turns on the all of the lower MOSFETs and pulls
SOFT-START, FAULT
AND CONTROL LOGIC
the output voltage below a level that might cause damage to
the load. The lower MOSFETs remain driven ON until VDIFF
falls below 400mV. The ISL6324A will continue to protect the
DUPLICATED FOR
NB AND CORE
1.8V
+
OVP
-
load in this fashion as long as the overvoltage condition
recurs. Once an overvoltage condition ends the ISL6324A
latches off, and must be reset by toggling POR, before a
soft-start can be re-initiated.
DAC + 250mV
+
-
OV
Pre-POR Overvoltage Protection
Prior to PVCC and VCC exceeding their POR levels, the
ISL6324A is designed to protect either load from any
VSEN
-
overvoltage events that may occur. This is accomplished by
+
UV
VDDPWRGD
means of an internal 10k Ω resistor tied from PHASE to
DAC - 300mV
ISL6324A INTERNAL CIRCUITRY
FIGURE 13. POWER-GOOD AND PROTECTION CIRCUITRY
Fault Monitoring and Protection
The ISL6324A actively monitors both CORE and NB output
voltages and currents to detect fault conditions. Fault
monitors trigger protective measures to prevent damage to
either load. One common power-good indicator is provided
for linking to external system monitors. The schematic in
Figure 13 outlines the interaction between the fault monitors
and the power good signal.
Power-Good Signal
The power good pin (VDDPWRGD) is an open-drain logic
output that signals whether or not the ISL6324A is regulating
both NB and CORE output voltages within the proper levels,
and whether any fault conditions exist. This pin should be
tied to a +5V source through a resistor.
During shutdown and soft-start, VDDPWRGD pulls low and
releases high after a successful soft-start and both output
voltages are operating between the undervoltage and
overvoltage limits. VDDPWRGD transitions low when an
undervoltage, overvoltage, or overcurrent condition is
detected on either regulator output or when the controller is
disabled by a POR reset or EN. In the event of an
overvoltage or overcurrent condition, the controller latches
off and VDDPWRGD will not return high. Pending a POR
reset of the ISL6324A and successful soft-start, the
VDDPWRGD will return high.
23
LGATE, which turns on the lower MOSFET to control the
output voltage until the overvoltage event ceases or the input
power supply cuts off. For complete protection, the low side
MOSFET should have a gate threshold well below the
maximum voltage rating of the load/microprocessor.
In the event that during normal operation the PVCC or VCC
voltage falls back below the POR threshold, the pre-POR
overvoltage protection circuitry reactivates to protect from
any more pre-POR overvoltage events.
Undervoltage Detection
The undervoltage threshold is set at VDAC - 300mV typical.
When the output voltage (VSEN-RGND) is below the
undervoltage threshold, VDDPWRGD gets pulled low. No
other action is taken by the controller. VDDPWRGD will
return high if the output voltage rises above VDAC - 250mV
typical.
Open Sense Line Protection
In the case that either of the remote sense lines, VSEN or
GND, become open, the ISL6324A is designed to detect this
and shut down the controller. This event is detected by
monitoring small currents that are fed out the VSEN and
RGND pins. In the event of an open sense line fault, the
controller will continue to remain off until the fault goes away,
at which point the controller will re-initiate a soft-start
sequence.
Overcurrent Protection
The ISL6324A takes advantage of the proportionality
between the load current and the average current, I AVG , to
detect an overcurrent condition. See “Continuous Current
FN6880.2
May 14, 2010
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相关代理商/技术参数 |
参数描述 |
|---|---|
| ISL6324ACRZ-TR5381 | 制造商:Intersil Corporation 功能描述:4+1 PHASE CONT., CORE + NORTHBRIDGE, PROG PSI, 3.4MHZ SVI, 5 - Tape and Reel 制造商:Intersil Corporation 功能描述:IC HYBRID CTRLR PWM DUAL 48QFN |
| ISL6324AIRZ | 功能描述:IC HYBRID CTRLR PWM DUAL 48QFN RoHS:是 类别:集成电路 (IC) >> PMIC - 稳压器 - 专用型 系列:- 标准包装:43 系列:- 应用:控制器，Intel VR11 输入电压:5 V ~ 12 V 输出数:1 输出电压:0.5 V ~ 1.6 V 工作温度:-40°C ~ 85°C 安装类型:表面贴装 封装/外壳:48-VFQFN 裸露焊盘 供应商设备封装:48-QFN（7x7） 包装:管件 |
| ISL6324AIRZR5381 | 制造商:Intersil Corporation 功能描述:4+1 PHASE CONTROLLER, CORE + NORTHBRIDGE, PROG PSI, 3.4MHZ S - Rail/Tube 制造商:Intersil Corporation 功能描述:IC HYBRID CTRLR PWM DUAL 48QFN |
| ISL6324AIRZ-T | 功能描述:IC HYBRID CTRLR PWM DUAL 48QFN RoHS:是 类别:集成电路 (IC) >> PMIC - 稳压器 - 专用型 系列:- 标准包装:43 系列:- 应用:控制器，Intel VR11 输入电压:5 V ~ 12 V 输出数:1 输出电压:0.5 V ~ 1.6 V 工作温度:-40°C ~ 85°C 安装类型:表面贴装 封装/外壳:48-VFQFN 裸露焊盘 供应商设备封装:48-QFN（7x7） 包装:管件 |
| ISL6324AIRZ-TR5381 | 制造商:Intersil Corporation 功能描述:4+1 PHASE CONTROLLER, CORE + NORTHBRIDGE, PROG PSI, 3.4MHZ S - Tape and Reel 制造商:Intersil Corporation 功能描述:IC HYBRID CTRLR PWM DUAL 48QFN |
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