参数资料
| 型号： | ISL6324ACRZ-T |
| 厂商： | Intersil |
| 文件页数： | 35/40页 |
| 文件大小： | 0K |
| 描述： | IC HYBRID CTRLR PWM DUAL 48QFN |
| 标准包装： | 4,000 |
| 应用： | 控制器，AMD SVI |
| 输入电压： | 5 V ~ 12 V |
| 输出数： | 2 |
| 输出电压： | 最高 2V |
| 工作温度： | 0°C ~ 70°C |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 48-VFQFN 裸露焊盘 |
| 供应商设备封装： | 48-QFN（7x7） |
| 包装： | 带卷 (TR) |
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ISL6324A
-------------------------------- ≤ f 0 < -------------------------------------
C 2
Case 2:
1 1
2 ? π ? L ? C 2 ? π ? C ? ESR
V P-P ? ( 2 ? π ) ? f 0 ? L ? C
R C
C C
COMP
2 2
0.66 ? V
R C = R FB ? ------------------------------------------------------------------
IN
(EQ. 51)
C C = ---------------------------------------------------------------------------------------
P-P ? R FB ?
( 2 ? π ) 2 ? f 2 ? V L ? C
f 0 > -------------------------------------
R C = R FB ? ----------------------------------------------
C 1
R 1
R FB
FB
VSEN
ISL6324A
Case 3:
0.66 ? V IN
0
1
2 ? π ? C ? ESR
2 ? π ? f 0 ? V P-P ? L
0.66 ? V IN ? ESR
2 ? π ? V P-P ? R FB ? f 0 ? L
.
FIGURE 24. COMPENSATION CIRCUIT WITHOUT LOAD-LINE
REGULATION
0.66 ? V IN ? ESR ? C
C C = ------------------------------------------------------------------
R 1 = R FB ? --------------------------------------------
C 1 = --------------------------------------------
C 2 = ---------------------------------------------------------------------------------------------------------
HF ? ( L ? C ) ? R FB ? V P – P
( 2 ? π ) 2 ? f ? f
C ? ESR
L ? C – C ? ESR
L ? C – C ? ESR
R FB
0.75 ? V IN
0
(EQ. 50)
The output inductors and the output capacitor bank together
to form a low-pass filter responsible for smoothing the
pulsating voltage at the phase nodes. The output filter also
must provide the transient energy until the regulator can
respond. Because it has a low bandwidth compared to the
switching frequency, the output filter limits the system
transient response. The output capacitors must supply or
sink load current while the current in the output inductors
increases or decreases to meet the demand.
V PP ? ? 2 π ? ? f 0 ? f HF ? L ? C ? R FB
R C = -----------------------------------------------------------------------------------------
0.75 ? V ? ( 2 ? π ? f HF ? L ? C – 1 )
( 2 ? π ) 2 ? f 0 ? f HF ? ( L ? C ) ? R FB ? V P – P
2
? ?
IN
0.75 ? V IN ? ( 2 ? π ? f HF ? L ? C – 1 )
C C = ---------------------------------------------------------------------------------------------------------
In the solutions to the compensation equations, there is a
single degree of freedom. For the solutions presented in
Equation 51, R FB is selected arbitrarily. The remaining
compensation components are then selected according to
Equation 51.
In Equation 51, L is the per-channel filter inductance divided
by the number of active channels; C is the sum total of all
output capacitors; ESR is the equivalent-series resistance of
the bulk output-filter capacitance; and V P-P is the peak-to-
peak sawtooth signal amplitude as described in “Electrical
Output Filter Design
In high-speed converters, the output capacitor bank is usually
the most costly (and often the largest) part of the circuit.
Output filter design begins with minimizing the cost of this part
of the circuit. The critical load parameters in choosing the
output capacitors are the maximum size of the load step, Δ I,
the load-current slew rate, di/dt, and the maximum allowable
output-voltage deviation under transient loading, Δ V MAX .
Capacitors are characterized according to their capacitance,
ESR, and ESL (equivalent series inductance).
At the beginning of the load transient, the output capacitors
supply all of the transient current. The output voltage will
initially deviate by an amount approximated by the voltage
drop across the ESL. As the load current increases, the
voltage drop across the ESR increases linearly until the load
current reaches its final value. The capacitors selected must
have sufficiently low ESL and ESR so that the total output
voltage deviation is less than the allowable maximum.
Neglecting the contribution of inductor current and regulator
response, the output voltage initially deviates by an amount
-------------------------------- > f 0
R C = R FB ? ----------------------------------------------------------
2 ? π ? V P-P ? R FB ? f 0
Δ V ≈ ESL ? ----- + ESR ? Δ I
(EQ. 52)
Case 1:
1
2 ? π ? L ? C
2 ? π ? f 0 ? V P-P ? L ? C
0.66 ? V IN
0.66 ? V IN
C C = ------------------------------------------------------
35
as shown in Equation 52:
di
dt
The filter capacitor must have sufficiently low ESL and ESR
so that Δ V < Δ V MAX .
Most capacitor solutions rely on a mixture of high frequency
capacitors with relatively low capacitance in combination
with bulk capacitors having high capacitance but limited
high-frequency performance. Minimizing the ESL of the
FN6880.2
May 14, 2010
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相关代理商/技术参数 |
参数描述 |
|---|---|
| ISL6324ACRZ-TR5381 | 制造商:Intersil Corporation 功能描述:4+1 PHASE CONT., CORE + NORTHBRIDGE, PROG PSI, 3.4MHZ SVI, 5 - Tape and Reel 制造商:Intersil Corporation 功能描述:IC HYBRID CTRLR PWM DUAL 48QFN |
| ISL6324AIRZ | 功能描述:IC HYBRID CTRLR PWM DUAL 48QFN RoHS:是 类别:集成电路 (IC) >> PMIC - 稳压器 - 专用型 系列:- 标准包装:43 系列:- 应用:控制器，Intel VR11 输入电压:5 V ~ 12 V 输出数:1 输出电压:0.5 V ~ 1.6 V 工作温度:-40°C ~ 85°C 安装类型:表面贴装 封装/外壳:48-VFQFN 裸露焊盘 供应商设备封装:48-QFN（7x7） 包装:管件 |
| ISL6324AIRZR5381 | 制造商:Intersil Corporation 功能描述:4+1 PHASE CONTROLLER, CORE + NORTHBRIDGE, PROG PSI, 3.4MHZ S - Rail/Tube 制造商:Intersil Corporation 功能描述:IC HYBRID CTRLR PWM DUAL 48QFN |
| ISL6324AIRZ-T | 功能描述:IC HYBRID CTRLR PWM DUAL 48QFN RoHS:是 类别:集成电路 (IC) >> PMIC - 稳压器 - 专用型 系列:- 标准包装:43 系列:- 应用:控制器，Intel VR11 输入电压:5 V ~ 12 V 输出数:1 输出电压:0.5 V ~ 1.6 V 工作温度:-40°C ~ 85°C 安装类型:表面贴装 封装/外壳:48-VFQFN 裸露焊盘 供应商设备封装:48-QFN（7x7） 包装:管件 |
| ISL6324AIRZ-TR5381 | 制造商:Intersil Corporation 功能描述:4+1 PHASE CONTROLLER, CORE + NORTHBRIDGE, PROG PSI, 3.4MHZ S - Tape and Reel 制造商:Intersil Corporation 功能描述:IC HYBRID CTRLR PWM DUAL 48QFN |
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