参数资料
| 型号： | ISL6324CRZ-T |
| 厂商： | Intersil |
| 文件页数： | 13/38页 |
| 文件大小： | 0K |
| 描述： | IC HYBRID CTRLR PWM DUAL 48-QFN |
| 标准包装： | 4,000 |
| 应用： | 控制器，AMD SVI |
| 输入电压： | 5 V ~ 12 V |
| 输出数： | 2 |
| 输出电压： | 最高 2V |
| 工作温度： | 0°C ~ 70°C |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 48-VFQFN 裸露焊盘 |
| 供应商设备封装： | 48-QFN（7x7） |
| 包装： | 带卷 (TR) |
第1页第2页第3页第4页第5页第6页第7页第8页第9页第10页第11页第12页当前第13页第14页第15页第16页第17页第18页第19页第20页第21页第22页第23页第24页第25页第26页第27页第28页第29页第30页第31页第32页第33页第34页第35页第36页第37页第38页
ISL6324
inductor current, I L . This sensed current, I SEN , is simply a
EXTERNAL CIRCUIT
APA
ISL6324 INTERNAL CIRCUIT
scaled version of the inductor current.
C APA
R APA
V APA,TRIP
COMP
100μA
LOW
PASS
FILTER
+
APA
-
TO APA
CIRCUITRY
PWM
SWITCHING PERIOD
ERROR
AMPLIFIER
FIGURE 3. ADAPTIVE PHASE ALIGNMENT DETECTION
The APA trip level is the amount of DC offset between the
COMP pin and the APA pin. This is the voltage excursion
that the APA and COMP pins must have during a transient
event to activate the Adaptive Phase Alignment circuitry.
This APA trip level is set through a resistor, R APA , that
connects from the APA pin to the COMP pin. A 100μA
current flows across R APA into the APA pin to set the APA
trip level as described in Equation 4. An APA trip level of
500mV is recommended for most applications. A 0.1μF
capacitor, C APA , should also be placed across the R APA
resistor to help with noise immunity.
I L
I SEN
TIME
FIGURE 4. CONTINUOUS CURRENT SAMPLING
The ISL6324 supports Inductor DCR current sensing to
continuously sample each channel’s current for channel-current
balance. The internal circuitry, shown in Figure 6 represents
Channel N of an N-Channel converter. This circuitry is repeated
for each channel in the converter, but may not be active
depending on how many channels are operating.
V APA , TRIP = R APA ? 100 × 10
– 6
(EQ. 4)
Inductor windings have a characteristic distributed
PWM Operation
The timing of each core channel is set by the number of
active channels. Channel detection on the ISEN3- and
ISEN4- pins selects 2-channel to 4-channel operation for the
ISL6324. The switching cycle is defined as the time between
resistance or DCR (Direct Current Resistance). For
simplicity, the inductor DCR is considered as a separate
lumped quantity, as shown in Figure 6. The channel current
I Ln , flowing through the inductor, passes through the DCR.
Equation 5 shows the S-domain equivalent voltage, V L ,
across the inductor.
V L ( s ) = I L ? ( s ? L + DCR )
PWM pulse termination signals of each channel. The cycle
time of the pulse signal is the inverse of the switching
n
(EQ. 5)
frequency set by the resistor between the FS pin and
ground. The PWM signals command the MOSFET driver to
turn on/off the channel MOSFETs.
For 4-channel operation, the channel firing order is 4-3-2-1:
PWM3 pulse happens 1/4 of a cycle after PWM4, PWM2
A simple R-C network across the inductor (R 1 , R 2 and C)
extracts the DCR voltage, as shown in Figure 6. The voltage
across the sense capacitor, V C , can be shown to be
proportional to the channel current I Ln , shown in Equation 6.
? ------------- + 1 ?
V C ( s ) = -------------------------------------------------------- ? K ? DCR ? I L
? ( R 1 ? R 2 ) ?
R 2
output follows another 1/4 of a cycle after PWM3, and
PWM1 delays another 1/4 of a cycle after PWM2. For
3-channel operation, the channel firing order is 3-2-1.
Connecting ISEN4- to VCC selects 3-channel operation and
the pulse times are spaced in 1/3 cycle increments. If ISEN3- is
connected to VCC, 2- channel operation is selected and the
PWM2 pulse happens 1/2 of a cycle after PWM1 pulse.
s ? L
? DCR ?
? s ? ------------------------ ? C + 1 ?
? R 1 + R 2 ?
Where:
K = ---------------------
R 2 + R 1
n
(EQ. 6)
(EQ. 7)
Continuous Current Sampling
In order to realize proper current-balance, the currents in
each channel are sampled continuously every switching
cycle. During this time, the current-sense amplifier uses the
ISEN inputs to reproduce a signal proportional to the
13
If the R-C network components are selected such that the
RC time constant matches the inductor L/DCR time constant
(see Equation 8), then V C is equal to the voltage drop across
the DCR multiplied by the ratio of the resistor divider, K. If a
resistor divider is not being used, the value for K is 1.
FN6518.2
September 25, 2008
相关PDF资料 |
PDF描述 |
|---|---|
| LT1963AEFE-3.3#PBF | IC REG LDO 3.3V 1.5A 16TSSOP |
| HIP6004DCRZ-T | IC CTRLR PWM VOLTAGE MON 20-QFN |
| LT1963AEFE-1.8#PBF | IC REG LDO 1.8V 1.5A 16TSSOP |
| HIP6004BCRZ-T | IC CTRLR PWM VOLTAGE MON 20-QFN |
| ADP1710AUJZ-3.0-R7 | IC REG LDO 3V .15A TSOT-23-5 |
相关代理商/技术参数 |
参数描述 |
|---|---|
| ISL6324IRZ | 功能描述:IC HYBRID CTRLR PWM DUAL 48-QFN RoHS:是 类别:集成电路 (IC) >> PMIC - 稳压器 - 专用型 系列:- 标准包装:43 系列:- 应用:控制器，Intel VR11 输入电压:5 V ~ 12 V 输出数:1 输出电压:0.5 V ~ 1.6 V 工作温度:-40°C ~ 85°C 安装类型:表面贴装 封装/外壳:48-VFQFN 裸露焊盘 供应商设备封装:48-QFN（7x7） 包装:管件 |
| ISL6324IRZ-T | 功能描述:IC HYBRID CTRLR PWM DUAL 48-QFN RoHS:是 类别:集成电路 (IC) >> PMIC - 稳压器 - 专用型 系列:- 标准包装:43 系列:- 应用:控制器，Intel VR11 输入电压:5 V ~ 12 V 输出数:1 输出电压:0.5 V ~ 1.6 V 工作温度:-40°C ~ 85°C 安装类型:表面贴装 封装/外壳:48-VFQFN 裸露焊盘 供应商设备封装:48-QFN（7x7） 包装:管件 |
| ISL6326AIRZ | 制造商:Rochester Electronics LLC 功能描述: 制造商:Intersil Corporation 功能描述: |
| ISL6326BCRZ | 功能描述:电流型 PWM 控制器 W/ANNEAL 4-PHS VR11 CNTRLR COM RoHS:否 制造商:Texas Instruments 开关频率:27 KHz 上升时间: 下降时间: 工作电源电压:6 V to 15 V 工作电源电流:1.5 mA 输出端数量:1 最大工作温度:+ 105 C 安装风格:SMD/SMT 封装 / 箱体:TSSOP-14 |
| ISL6326BCRZ-T | 功能描述:电流型 PWM 控制器 W/ANNEAL 4-PHS VR11 CNTRLR COM RoHS:否 制造商:Texas Instruments 开关频率:27 KHz 上升时间: 下降时间: 工作电源电压:6 V to 15 V 工作电源电流:1.5 mA 输出端数量:1 最大工作温度:+ 105 C 安装风格:SMD/SMT 封装 / 箱体:TSSOP-14 |
发布紧急采购，3分钟左右您将得到回复。