参数资料
| 型号： | ISL6324CRZ-T |
| 厂商： | Intersil |
| 文件页数： | 21/38页 |
| 文件大小： | 0K |
| 描述： | IC HYBRID CTRLR PWM DUAL 48-QFN |
| 标准包装： | 4,000 |
| 应用： | 控制器，AMD SVI |
| 输入电压： | 5 V ~ 12 V |
| 输出数： | 2 |
| 输出电压： | 最高 2V |
| 工作温度： | 0°C ~ 70°C |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 48-VFQFN 裸露焊盘 |
| 供应商设备封装： | 48-QFN（7x7） |
| 包装： | 带卷 (TR) |
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ISL6324
.
-
17.5μA
V NB
400mV/DIV
V CORE
400mV/DIV
OCL
+
I 1
12.5μA
-
OCP
REPEAT FOR EACH
CORE CHANNEL
EN
TDA
TDB
I NB
+
-
OCP
12.5μA
5V/DIV
VDDPWRGD
NB ONLY
+
I AVG
CORE ONLY
5V/DIV
SOFT-START, FAULT
AND CONTROL LOGIC
100μs/DIV
FIGURE 11. SOFT-START WAVEFORMS
DUPLICATED FOR
NB AND CORE
1.8V
+
OVP
Pre-Biased Soft-Start
-
The ISL6324 also has the ability to start up into a
pre-charged output, without causing any unnecessary
disturbance. The FB pin is monitored during soft-start, and
DAC + 250mV
+
-
OV
should it be higher than the equivalent internal ramping
reference voltage, the output drives hold both MOSFETs off.
VSEN
-
UV
Once the internal ramping reference exceeds the FB pin
potential, the output drives are enabled, allowing the output to
ramp from the pre-charged level to the final level dictated by
DAC - 300mV
+
VDDPWRGD
ISL6324 INTERNAL CIRCUITRY
the DAC setting. Should the output be pre-charged to a level
exceeding the DAC setting, the output drives are enabled at
the end of the soft-start period, leading to an abrupt correction
in the output voltage down to the DAC-set level.
Both CORE and NB output support start-up into a
pre-charged output.
OUTPUT PRECHARGED
ABOVE DAC LEVEL
OUTPUT PRECHARGED
BELOW DAC LEVEL
V CORE
400mV/DIV
EN
5V/DIV
100μs/DIV
FIGURE 12. SOFT-START WAVEFORMS FOR ISL6324-BASED
MULTIPHASE CONVERTER
21
FIGURE 13. POWER-GOOD AND PROTECTION CIRCUITRY
Fault Monitoring and Protection
The ISL6324 actively monitors both CORE and NB output
voltages and currents to detect fault conditions. Fault
monitors trigger protective measures to prevent damage to
either load. One common power good indicator is provided
for linking to external system monitors. The schematic in
Figure 13 outlines the interaction between the fault monitors
and the power good signal.
Power-Good Signal
The power-good pin (VDDPWRGD) is an open-drain logic
output that signals whether or not the ISL6324 is regulating
both NB and CORE output voltages within the proper levels,
and whether any fault conditions exist. This pin should be
tied to a +5V source through a resistor.
During shutdown and soft-start, VDDPWRGD pulls low and
releases high after a successful soft-start and both output
voltages are operating between the undervoltage and
overvoltage limits. VDDPWRGD transitions low when an
undervoltage, overvoltage, or overcurrent condition is
detected on either output or when the controller is disabled
by a POR reset or EN. In the event of an overvoltage or
overcurrent condition, the controller latches off and
VDDPWRGD will not return high. Pending a POR reset of
the ISL6324 and successful soft-start, the VDDPWRGD will
return high.
FN6518.2
September 25, 2008
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相关代理商/技术参数 |
参数描述 |
|---|---|
| ISL6324IRZ | 功能描述:IC HYBRID CTRLR PWM DUAL 48-QFN RoHS:是 类别:集成电路 (IC) >> PMIC - 稳压器 - 专用型 系列:- 标准包装:43 系列:- 应用:控制器，Intel VR11 输入电压:5 V ~ 12 V 输出数:1 输出电压:0.5 V ~ 1.6 V 工作温度:-40°C ~ 85°C 安装类型:表面贴装 封装/外壳:48-VFQFN 裸露焊盘 供应商设备封装:48-QFN（7x7） 包装:管件 |
| ISL6324IRZ-T | 功能描述:IC HYBRID CTRLR PWM DUAL 48-QFN RoHS:是 类别:集成电路 (IC) >> PMIC - 稳压器 - 专用型 系列:- 标准包装:43 系列:- 应用:控制器，Intel VR11 输入电压:5 V ~ 12 V 输出数:1 输出电压:0.5 V ~ 1.6 V 工作温度:-40°C ~ 85°C 安装类型:表面贴装 封装/外壳:48-VFQFN 裸露焊盘 供应商设备封装:48-QFN（7x7） 包装:管件 |
| ISL6326AIRZ | 制造商:Rochester Electronics LLC 功能描述: 制造商:Intersil Corporation 功能描述: |
| ISL6326BCRZ | 功能描述:电流型 PWM 控制器 W/ANNEAL 4-PHS VR11 CNTRLR COM RoHS:否 制造商:Texas Instruments 开关频率:27 KHz 上升时间: 下降时间: 工作电源电压:6 V to 15 V 工作电源电流:1.5 mA 输出端数量:1 最大工作温度:+ 105 C 安装风格:SMD/SMT 封装 / 箱体:TSSOP-14 |
| ISL6326BCRZ-T | 功能描述:电流型 PWM 控制器 W/ANNEAL 4-PHS VR11 CNTRLR COM RoHS:否 制造商:Texas Instruments 开关频率:27 KHz 上升时间: 下降时间: 工作电源电压:6 V to 15 V 工作电源电流:1.5 mA 输出端数量:1 最大工作温度:+ 105 C 安装风格:SMD/SMT 封装 / 箱体:TSSOP-14 |
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