参数资料
| 型号： | ISL6324CRZ-T |
| 厂商： | Intersil |
| 文件页数： | 9/38页 |
| 文件大小： | 0K |
| 描述： | IC HYBRID CTRLR PWM DUAL 48-QFN |
| 标准包装： | 4,000 |
| 应用： | 控制器，AMD SVI |
| 输入电压： | 5 V ~ 12 V |
| 输出数： | 2 |
| 输出电压： | 最高 2V |
| 工作温度： | 0°C ~ 70°C |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 48-VFQFN 裸露焊盘 |
| 供应商设备封装： | 48-QFN（7x7） |
| 包装： | 带卷 (TR) |
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ISL6324
Timing Diagram
t PDHUGATE
t RUGATE
UGATE
LGATE
t FLGATE
Functional Pin Description
VID1/SEL
This pin selects SVI or PVI mode operation based on the state
of the pin prior to enabling the ISL6324. If the pin is LO prior to
enable, the ISL6324 is in SVI mode and the dual purpose pins
[VID0/VFIXEN, VID2/SVC, VID3/SVD] use their SVI mode
related functions. If the pin held HI prior to enable, the
ISL6324 is in PVI mode and dual purpose pins use their VIDx
related functions to decode the correct DAC code.
VID0/VFIXEN
If VID1 is LO prior to enable [SVI Mode], the pin is functions
as the VFIXEN selection input from the AMD processor for
determining SVI mode versus VFIX mode of operation.
If VID1 is HI prior to enable [PVI Mode], the pin is used as
DAC input VID0. This pin has an internal 30μA pull-down
current applied to it at all times.
VID2/SVD
If VID1 is LO prior to enable [SVI Mode], this pin is the serial
VID data bi-directional signal to and from the master device on
AMD processor. If VID1 is HI prior to enable [PVI Mode], this
pin is used to decode the programmed DAC code for the
processor. In PVI mode, this pin has an internal 30μA pull-down
current applied to it. There is no pull-down current in SVI mode.
VID3/SVC
If VID1 is LO prior to enable [SVI Mode], this pin is the serial
VID clock input from the AMD processor. If VID1 is HI prior to
enable [PVI Mode], the ISL6324 is in PVI mode and this pin is
used to decode the programmed DAC code for the processor.
In PVI mode, this pin has an internal 30μA pull-down current
applied to it. There is no pull-down current in SVI mode.
VID4
This pin is active only when the ISL6324 is in PVI mode.
When VID1 is HI prior to enable, the ISL6324 decodes the
programmed DAC voltage required by the AMD processor.
This pin has an internal 30μA pull-down current applied to it at
all times.
VID5
This pin is active only when the ISL6324 is in PVI mode.
When VID1 is HI prior to enable, the ISL6324 decodes the
9
t FUGATE
t RLGATE
t PDHLGATE
programmed DAC voltage required by the AMD processor.
This pin has an internal 30μA pull-down current applied to it at
all times.
VCC
VCC is the bias supply for the ICs small-signal circuitry.
Connect this pin to a +5V supply and decouple using a
quality 0.1μF ceramic capacitor.
PVCC1_2
The power supply pin for the multiphase internal MOSFET
drivers. Connect this pin to any voltage from +5V to +12V
depending on the desired MOSFET gate-drive level.
Decouple this pin with a quality 1.0μF ceramic capacitor.
PVCC_NB
The power supply pin for the internal MOSFET driver for the
Northbridge controller. Connect this pin to any voltage from
+5V to +12V depending on the desired MOSFET gate-drive
level. Decouple this pin with a quality 1.0μF ceramic capacitor.
GND
GND is the bias and reference ground for the IC. The GND
connection for the ISL6324 is through the thermal pad on the
bottom of the package.
EN
This pin is a threshold-sensitive (approximately 0.85V) system
enable input for the controller. Held low, this pin disables both
CORE and NB controller operation. Pulled high, the pin
enables both controllers for operation.
When the EN pin is pulled high, the ISL6324 will be placed in
either SVI or PVI mode. The mode is determined by the
latched value of VID1 on the rising edge of the EN signal.
A third function of this pin is to provide driver bias monitor for
external drivers. A resistor divider with the center tap
connected to this pin from the drive bias supply prevents
enabling the controller before insufficient bias is provided to
external driver. The resistors should be selected such that
when the POR-trip point of the external driver is reached, the
voltage at this pin meets the mentioned threshold level.
FN6518.2
September 25, 2008
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相关代理商/技术参数 |
参数描述 |
|---|---|
| ISL6324IRZ | 功能描述:IC HYBRID CTRLR PWM DUAL 48-QFN RoHS:是 类别:集成电路 (IC) >> PMIC - 稳压器 - 专用型 系列:- 标准包装:43 系列:- 应用:控制器，Intel VR11 输入电压:5 V ~ 12 V 输出数:1 输出电压:0.5 V ~ 1.6 V 工作温度:-40°C ~ 85°C 安装类型:表面贴装 封装/外壳:48-VFQFN 裸露焊盘 供应商设备封装:48-QFN（7x7） 包装:管件 |
| ISL6324IRZ-T | 功能描述:IC HYBRID CTRLR PWM DUAL 48-QFN RoHS:是 类别:集成电路 (IC) >> PMIC - 稳压器 - 专用型 系列:- 标准包装:43 系列:- 应用:控制器，Intel VR11 输入电压:5 V ~ 12 V 输出数:1 输出电压:0.5 V ~ 1.6 V 工作温度:-40°C ~ 85°C 安装类型:表面贴装 封装/外壳:48-VFQFN 裸露焊盘 供应商设备封装:48-QFN（7x7） 包装:管件 |
| ISL6326AIRZ | 制造商:Rochester Electronics LLC 功能描述: 制造商:Intersil Corporation 功能描述: |
| ISL6326BCRZ | 功能描述:电流型 PWM 控制器 W/ANNEAL 4-PHS VR11 CNTRLR COM RoHS:否 制造商:Texas Instruments 开关频率:27 KHz 上升时间: 下降时间: 工作电源电压:6 V to 15 V 工作电源电流:1.5 mA 输出端数量:1 最大工作温度:+ 105 C 安装风格:SMD/SMT 封装 / 箱体:TSSOP-14 |
| ISL6326BCRZ-T | 功能描述:电流型 PWM 控制器 W/ANNEAL 4-PHS VR11 CNTRLR COM RoHS:否 制造商:Texas Instruments 开关频率:27 KHz 上升时间: 下降时间: 工作电源电压:6 V to 15 V 工作电源电流:1.5 mA 输出端数量:1 最大工作温度:+ 105 C 安装风格:SMD/SMT 封装 / 箱体:TSSOP-14 |
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