参数资料
型号: ISL6326CRZ-T
厂商: Intersil
文件页数: 18/30页
文件大小: 0K
描述: IC REG CTRLR BUCK PWM VM 40-QFN
标准包装: 4,000
PWM 型: 电压模式
输出数: 1
频率 - 最大: 275kHz
占空比: 25%
电源电压: 4.75 V ~ 5.25 V
降压:
升压:
回扫:
反相:
倍增器:
除法器:
Cuk:
隔离:
工作温度: 0°C ~ 70°C
封装/外壳: 40-VFQFN 裸露焊盘
包装: 带卷 (TR)
ISL6326
Load-Line Regulation
Some microprocessor manufacturers require a
precisely-controlled output resistance. This dependence of
output voltage on load current is often termed “droop” or
“load line” regulation. By adding a well controlled output
impedance, the output voltage can effectively be level shifted
in a direction which works to achieve the load-line regulation
required by these manufacturers.
In other cases, the designer may determine that a more
cost-effective solution can be achieved by adding droop.
Droop can help to reduce the output voltage spike that
results from fast load-current demand changes.
The magnitude of the spike is dictated by the ESR and ESL
Output Voltage Offset Programming
The ISL6326 allows the designer to accurately adjust the
offset voltage. When a resistor, R OFS , is connected between
OFS to VCC, the voltage across it is regulated to 1.6V. This
causes a proportional current (I OFS ) to flow into OFS. If
R OFS is connected to ground, the voltage across it is
regulated to 0.4V, and I OFS flows out of OFS. A resistor
between DAC and REF, R REF , is selected so that the
product (I OFS x R OFS ) is equal to the desired offset voltage.
These functions are shown in Figure 6.
Once the desired output offset voltage has been determined,
use Equations 11 and 12 to set R OFS :
For Positive Offset (connect R OFS to VCC):
R OFS = ------------------------------
R OFS = ------------------------------
of the output capacitors selected. By positioning the no-load
voltage level near the upper specification limit, a larger
negative spike can be sustained without crossing the lower
limit. By adding a well controlled output impedance, the
output voltage under load can effectively be level shifted
down so that a larger positive spike can be sustained without
crossing the upper specification limit.
As shown in Figure 5, a current proportional to the average
current of all active channels (I AVG ) flows from FB through a
load-line regulation resistor R FB . The resulting voltage drop
across R FB is proportional to the output current, effectively
creating an output voltage droop with a steady-state value
defined as Equation 8:
1.6 × R REF
V OFFSET
For Negative Offset (connect R OFS to GND):
0.4 × R REF
V OFFSET
FB
DYNAMIC
VID D/A
(EQ. 11)
(EQ. 12)
DAC
V DROOP = I AVG R FB
(EQ. 8)
-
R REF
E/A
The regulated output voltage is reduced by the droop voltage
V DROOP . The output voltage as a function of load current is
derived by combining Equation 8 with the appropriate
sample current expression defined by the current sense
method employed in Equation 9.
+
+
-
REF
C REF
V OUT = V REF – V OFS – ? ------------- ------------------ R FB ?
? I OUT R X ?
? N R ISEN ?
(EQ. 9)
-
VCC
OR
GND
Where V REF is the reference voltage, V OFS is the
programmed offset voltage, I OUT is the total output current
of the converter, R ISEN is the sense resistor connected to
the ISEN+ pin, and R FB is the feedback resistor, N is the
1.6V
-
+
0.4V
+
-
+
ISL6326B
OFS
R OFS
active channel number, and R X is the DCR, or R SENSE
depending on the sensing method.
VCC
GND
Therefore the equivalent loadline impedance, i.e. Droop
impedance, is equal to Equation 10:
FIGURE 6. OUTPUT VOLTAGE OFFSET PROGRAMMING
R LL = ------------ ------------------
R ISEN
R FB R X
N
18
(EQ. 10)
FN9262.1
May 5, 2008
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