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| 型号： | ISL6326CRZ-T |
| 厂商： | Intersil |
| 文件页数： | 27/30页 |
| 文件大小： | 0K |
| 描述： | IC REG CTRLR BUCK PWM VM 40-QFN |
| 标准包装： | 4,000 |
| PWM 型： | 电压模式 |
| 输出数： | 1 |
| 频率 - 最大： | 275kHz |
| 占空比： | 25% |
| 电源电压： | 4.75 V ~ 5.25 V |
| 降压： | 是 |
| 升压： | 无 |
| 回扫： | 无 |
| 反相： | 无 |
| 倍增器： | 无 |
| 除法器： | 无 |
| Cuk： | 无 |
| 隔离： | 无 |
| 工作温度： | 0°C ~ 70°C |
| 封装/外壳： | 40-VFQFN 裸露焊盘 |
| 包装： | 带卷 (TR) |
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ISL6326
C 2
Output Filter Design
The output inductors and the output capacitor bank together
R C
C C
COMP
to form a low-pass filter responsible for smoothing the
pulsating voltage at the phase nodes. The output filter also
must provide the transient energy until the regulator can
C 1
FB
respond. Because it has a low bandwidth compared to the
switching frequency, the output filter necessarily limits the
system transient response. The output capacitor must
R 1
R FB
IDROOP
VDIFF
supply or sink load current while the current in the output
inductors increases or decreases to meet the demand.
In high-speed converters, the output capacitor bank is
usually the most costly (and often the largest) part of the
FIGURE 17. COMPENSATION CIRCUIT FOR ISL6326 BASED
CONVERTER WITHOUT LOAD-LINE
REGULATION
The first step is to choose the desired bandwidth, f 0 , of the
compensated system. Choose a frequency high enough to
assure adequate transient performance but not higher than
1/3 of the switching frequency. The type-III compensator has
an extra high-frequency pole, f HF . This pole can be used for
added noise rejection or to assure adequate attenuation at
the error-amplifier high-order pole and zero frequencies. A
good general rule is to choose f HF = 10f 0 , but it can be
higher if desired. Choosing f HF to be lower than 10f 0 can
cause problems with too much phase shift below the system
bandwidth.
In the solutions to the compensation equations, there is a
single degree of freedom. For the solutions presented in
Equation 36, R FB is selected arbitrarily. The remaining
compensation components are then selected.
circuit. Output filter design begins with minimizing the cost of
this part of the circuit. The critical load parameters in
choosing the output capacitors are the maximum size of the
load step, Δ I; the load-current slew rate, di/dt; and the
maximum allowable output voltage deviation under transient
loading, Δ V MAX . Capacitors are characterized according to
their capacitance, ESR, and ESL (equivalent series
inductance).
At the beginning of the load transient, the output capacitors
supply all of the transient current. The output voltage will
initially deviate by an amount approximated by the voltage
drop across the ESL. As the load current increases, the
voltage drop across the ESR increases linearly until the load
current reaches its final value. The capacitors selected must
have sufficiently low ESL and ESR so that the total output
voltage deviation is less than the allowable maximum.
Neglecting the contribution of inductor current and regulator
response, the output voltage initially deviates by an amount
in Equation 37:
R 1 = R FB -----------------------------------------
Δ V ≈ ( ESL ) ----- + ( ESR ) Δ I
C ( ESR )
LC – C ( ESR )
di
dt
(EQ. 37)
C 1 = -----------------------------------------
LC – C ( ESR )
R FB
The filter capacitor must have sufficiently low ESL and ESR
so that Δ V < Δ V MAX .
( 2 π ) 0 HF LCR FB V P-P
C 2 = --------------------------------------------------------------------
V PP ? 2 π ? f 0 f HF LCR FB
R C = ---------------------------------------------------------------------
? 2 π f
HF LC – 1 ?
?
0.75 V
0.75V IN
2 f f
2
? ?
IN
?
(EQ. 36)
Most capacitor solutions rely on a mixture of high-frequency
capacitors with relatively low capacitance in combination
with bulk capacitors having high capacitance but limited
high-frequency performance. Minimizing the ESL of the
high-frequency capacitors allows them to support the output
voltage as the current increases. Minimizing the ESR of the
bulk capacitors allows them to supply the increased current
0.75V IN ? 2 π f
( 2 π ) 2 f 0 f HF LCR FB V P-P
?
? HF LC – 1 ?
C C = --------------------------------------------------------------------
In Equation 36, L is the per-channel filter inductance divided
by the number of active channels; C is the sum total of all
output capacitors; ESR is the equivalent-series resistance of
the bulk output-filter capacitance; and V P-P is the sawtooth
signal amplitude as described in “Electrical Specifications”
27
with less output voltage deviation.
The ESR of the bulk capacitors also creates the majority of
the output voltage ripple. As the bulk capacitors sink and
source the inductor AC ripple current (see “Interleaving” on
page 10 and Equation 2), a voltage develops across the
bulk-capacitor ESR equal to I C(P-P) (ESR). Thus, once the
output capacitors are selected, the maximum allowable
ripple voltage, V P-P(MAX) , determines the lower limit on the
inductance.
FN9262.1
May 5, 2008
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相关代理商/技术参数 |
参数描述 |
|---|---|
| ISL6326CRZ-TR5453 | 制造商:Intersil Corporation 功能描述:STD. ISL6326CRZ-T W/GOLD BOND WIRE ONLY - Tape and Reel |
| ISL6326IRZ | 功能描述:电流型 PWM 控制器 W/ANNEAL 4-PHS VR11 CNTRLR IND RoHS:否 制造商:Texas Instruments 开关频率:27 KHz 上升时间: 下降时间: 工作电源电压:6 V to 15 V 工作电源电流:1.5 mA 输出端数量:1 最大工作温度:+ 105 C 安装风格:SMD/SMT 封装 / 箱体:TSSOP-14 |
| ISL6326IRZ-T | 功能描述:电流型 PWM 控制器 W/ANNEAL 4-PHS VR11 CNTRLR IND RoHS:否 制造商:Texas Instruments 开关频率:27 KHz 上升时间: 下降时间: 工作电源电压:6 V to 15 V 工作电源电流:1.5 mA 输出端数量:1 最大工作温度:+ 105 C 安装风格:SMD/SMT 封装 / 箱体:TSSOP-14 |
| ISL6327ACRZ | 功能描述:IC REG CTRLR BUCK PWM 48-QFN RoHS:是 类别:集成电路 (IC) >> PMIC - 稳压器 - DC DC 切换控制器 系列:- 产品培训模块:Lead (SnPb) Finish for COTS Obsolescence Mitigation Program 标准包装:2,500 系列:- PWM 型:电流模式 输出数:1 频率 - 最大:275kHz 占空比:50% 电源电压:18 V ~ 110 V 降压:无 升压:无 回扫:无 反相:无 倍增器:无 除法器:无 Cuk:无 隔离:是 工作温度:-40°C ~ 85°C 封装/外壳:8-SOIC（0.154"，3.90mm 宽） 包装:带卷 (TR) |
| ISL6327ACRZ-T | 功能描述:IC REG CTRLR BUCK PWM 48-QFN RoHS:是 类别:集成电路 (IC) >> PMIC - 稳压器 - DC DC 切换控制器 系列:- 产品培训模块:Lead (SnPb) Finish for COTS Obsolescence Mitigation Program 标准包装:2,500 系列:- PWM 型:电流模式 输出数:1 频率 - 最大:275kHz 占空比:50% 电源电压:18 V ~ 110 V 降压:无 升压:无 回扫:无 反相:无 倍增器:无 除法器:无 Cuk:无 隔离:是 工作温度:-40°C ~ 85°C 封装/外壳:8-SOIC（0.154"，3.90mm 宽） 包装:带卷 (TR) |
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