参数资料
型号: ISL6328IRZ
厂商: Intersil
文件页数: 15/33页
文件大小: 0K
描述: IC CTRLR PWM SYNC BUCK DL 48QFN
标准包装: 50
应用: 控制器,AMD SVI
输入电压: 5 V ~ 12 V
输出数: 2
输出电压: 0.0125 V ~ 1.55 V
工作温度: -40°C ~ 85°C
安装类型: *
封装/外壳: *
供应商设备封装: *
包装: *
ISL6328
A capacitor, C ISEN , should be placed between the ISENn+ pin and
ground. The value of the capacitor can be calculated using
representation of the load current. The load current is given by
Equation 14.
C ISEN = ---------------
I LOAD = 8 ? ------------------------ ? ---------------
R TC
Equation 11.
9.5ns
R ISEN
(EQ. 11)
V TCOMP2 R ISEN
DCR
(EQ. 14)
Where R ISEN is the current sense resistor value and DCR is the
DC resistance of the output inductors. It is recommended that a
high impedance buffer be used when monitoring the voltage on
the TCOMP2 pin.
I TC_IN
I ITC_OUT
Channel-Current Balance
One important benefit of multi-phase operation is the thermal
advantage gained by distributing the dissipated heat over
multiple devices and greater area. By doing this the designer
avoids the complexity of driving parallel MOSFETs and the
expense of using expensive heat sinks and exotic magnetic
materials.
R 1
R NTC
R 2
TCOMP1
R T (T)
TCOMP2
R TC = R T (25°C)
In order to realize the thermal advantage, it is important that
each channel in a multi-phase converter be controlled to carry
about the same amount of current at any load level. To achieve
this, the currents through each channel must be sampled every
PWM1
V COMP
-
-
I ER
I AVG 1.3
I 3
R 3
FIGURE 5. AVERAGE CURRENT TEMPERATURE
COMPENSATION
Temperature Compensated Current Sensing
As the load increases, the conduction losses in the output
inductors will cause the temperature of the inductors to rise. As
the inductor temperature rises, the DCR of the output inductors
will also rise. An increase in the DCR will result in an increase in
the sensed current even if the load current remains constant. To
counteract this error in the sensed current, the ISL6328 features
a temperature compensating circuit that utilizes an NTC resistor
to adjust the average current as inductor temperature increases.
Figure 5 shows the implementation of the ISL6328 average
current temperature compensation. The temperature dependent
resistor, R T (T), is a combination of resistors and an NTC which
create an approximate linearization of the NTC resistor (refer to
Equation 12). Resistors R 1 , R 2 and R 3 should be adjusted so that
Equation 13 is satisfied.
switching cycle. The sampled currents, I n , from each active
channel are summed together and divided by the number of
active channels. The resulting cycle average current, I AVG ,
provides a measure of the total load-current demand on the
converter during each switching cycle. Channel-current balance is
achieved by comparing the sampled current of each channel to
the cycle average current, and making the proper adjustment to
each channel pulse width based on the error. Intersil’s patented
current-balance method is illustrated in Figure 6, with error
correction for Channel 1 represented. In the figure, the cycle
average current, I AVG , is compared with the Channel 1 sample,
I 1 , to create an error signal I ER .
+
+ TO GATE
MODULATOR CONTROL
RAMP LOGIC
WAVEFORM
FILTER f(s)
I 4
Σ
- N
+
I 2
R T ( T ) = R 3 + -----------------------------------------
1 1
R 1 + R NTC
R 2
R T ( T ) = ---------------------------------- ? R TC
1
--------------------------- + -------
DCR ( +25 ° C )
DCR ( T )
(EQ. 12)
(EQ. 13)
I 1
NOTE: CHANNELS 2, 3 AND 4 ARE OPTIONAL.
FIGURE 6. CHANNEL-1 PWM FUNCTION AND CURRENT-
BALANCE ADJUSTMENT
Where R TC = R T (+25°C)
LOAD MONITORING
The TCOMP2 pin can be utilized to monitor the load current. The
voltage across the R TC resistor is a temperature compensated
15
The filtered error signal modifies the pulse width commanded by
V COMP to correct any unbalance and force I ER toward zero. The
same method for error signal correction is applied to each active
channel.
Serial VID Interface (SVI)
The on-board Serial VID interface (SVI) circuitry allows the
processor to directly drive the core voltage and Northbridge
voltage reference level within the ISL6328. The SVC and SVD
FN7621.1
June 7, 2011
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